LPD MIO Pin Table

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English
Table 1. LPD MIO Pin Assignments (Bank 502)
LPD MIO Pins: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Controllers in Low-power Domain
LPD_GPIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
GEM 0 RGMII TX CLK TXD 0 TXD 1 TXD 2 TXD 3 TX CTL RX CLK RXD 0 RXD 1 RXD 2 RXD 3 RX CTL – – – – – – – – – – – – – –
GEM 1 RGMII – – – – – – – – – – – – TX CLK TXD 0 TXD 1 TXD 2 TXD 3 TX CTL RX CLK RXD 0 RXD 1 RXD 2 RXD 3 RX CTL – –
GEM n MDIO – – – – – – – – – – – – – – – – – – – – – – – – CLK DATA
GEM TSU – – – – – – – – – – – – – – – – – – – – – – – – CLK CLK
CAN FD 0 – – RX TX – – RX TX – – RX TX – – RX TX – – RX TX – – RX TX – –
CAN FD 1 TX RX – – TX RX – – TX RX – – TX RX – – TX RX – – TX RX – – TX RX
LPD_I2C0 – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – –
LPD_I2C1 SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA
SYSMON_I2C SCL SDA SMB – SCL SDA SMB – – SCL SDA SMB – SCL SDA SMB – – SCL SDA SMB – – SCL SDA SMB
PCIe resets – – – – – – – – – – – – – – – – – – RST 0 RST 1 – – – – – –
SPI0 SCLK CS2 CS1 CS0 MISO MOSI – – – – – – SCLK CS2 CS1 CS0 MISO MOSI – – – – – – – –
SPI1 – – – – – – SCLK CS2 CS1 CS0 MISO MOSI – – – – – – SCLK CS2 CS1 CS0 MISO MOSI – –
Trace Port – – CTL D 0 D 1 D 2 CLK D 3 D 4 D 5 D 6 D 7 D 8 D 9 – – – – D 10 D 11 D 12 D 13 D 14 D 15 – –
TTC n CLK 3 WA 3 CLK 2 WA 2 CLK 1 WA 1 CLK 0 WA 0 CLK 3 WA 3 CLK 2 WA 2 CLK 1 WA 1 CLK 0 WA 0 CLK 3 WA 3 CLK 2 WA 2 CLK 1 WA 1 CLK 0 WA 0 – –
UART0 RXD TXD CTS RTS – – – – RXD TXD CTS RTS – – – – RXD TXD CTS RTS – – – – – –
UART1 – – – – TXD RXD RTS CTS – – – – TXD RXD RTS CTS – – – – TXD RXD RTS CTS – –
LPD SWDT CLK RST1 PEND INT WS0 WS1 – – – – – – CLK RST1 PEND INT WS0 WS1 – – – – – – – –
FPD SWDT – – – – – – CLK RST1 PEND INT WS0 WS1 – – – – – – CLK RST1 PEND INT WS0 WS1 – –