For the SDR-50, SDR-104, and HS-200 modes, automatic RX tuning is performed. The controller uses a built-in algorithm to issue a series of tuning commands to the attached device. Each access uses a different tap delay setting to find the center of the band of successful data transitions. The tap located in the center of the band is selected.
In other modes (such as DDR50), the manual tuning of the SD_CLK can be performed using the DLL clock and module register controls, see the Manual DLL Programming Sequence section.
Auto Tuning Note
After auto-tuning, one of the following must occur before sending any command sequence including CMD19, CMD21, or any other command sequence. An example for SD0 is as follows:
- SD_eMMC CLK_CTRL [IntClkStable, 1] reads = 1
- PMC_IOP_SLCR SD0_DLL_Ctrl [DLL_PSDone] reads = 1
The maximum number of tap delays in DLL mode (phases of the clock) is 180, but the useful number of tap delays is reduced as the clock frequency goes up.