Permission and TrustZone Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English
The aperture permission register structure enumerates the permission settings on each protected peripheral. Each APERPERM_xxx register entry contains the information listed in the following table.
Table 1. Aperture Permission Register
Field Name Bit Field Description

SMID profile permission. Each bit correspond to the SMID_[0:19] registers. The [permission] field helps to determine if the transaction request characterized by a SMID register is permitted.

0: Not allowed

1: Allowed

A 1 in bit position n (n < m) indicates that the nth entry in the SMID list has permission to access the aperture. This check is further qualified by parity and TrustZone checks.


0: Only secure transactions are allowed

1: Secure or non-secure transactions are allowed

PARITY 28 Write even parity for bit [27] and bits [19:15]
29 Write even parity for bits [14:10]
30 Write even parity for bits [9:5]
31 Write even parity for bits [4:0]

Parity on RAM-based Aperture Permission Registers

The aperture permission registers are based in RAM memory. If the parity option is enabled, the parity bits must be computed and written by the software for each aperture permission register.

To provide integrity, the [permission] and [trustzone] bit fields are even parity protected and continuously read by the hardware. If the aperture permission parity is enabled ( CTRL [APER_PARITY_EN] = 1) and a parity is detected in the RAM, the aperture parity interrupt is asserted and the aperture permission register is disabled.