The following table lists the control and status registers.
Note: These registers are defined with
multiple data widths. However, all registers are accessed as 32-bit read/write
transfers with addresses aligned on a 32-bit address boundary.
| Register Name | Width | Offset Address | Access Type | Description |
|---|---|---|---|---|
| Configuration and Control | ||||
| PRESENT_STATE | 32 |
0x024
|
R | Current status of signals and states |
| HOST_CTRL1 | 8 |
0x028
|
RW |
Program DMA modes, LED control, data transfer width, high-speed enable, card detect test level, and signal selection |
| HOST_CTRL2 | 16 |
0x03E
|
RW | Program UHS select mode, driver strength, execute tuning, sampling clock select, asynchronous interrupt enable, and preset value enable |
| POWER_CTRL | 8 |
0x029
|
RW | Program SD bus power and voltage level |
| BLOCK_GAP_CTRL | 8 |
0x02A
|
RW, WTC | Program block gap request, read wait control, and interrupt at block gap |
| WAKE_UP_CTRL | 8 |
0x02B
|
RW | Program wake-up functionality |
| TIMEOUT_CTRL | 8 |
0x02E
|
RW | Data timeout counter value |
| Controller Reset | ||||
| SW_RST | 8 |
0x02F
|
Clear on write | Program software reset for data, command, and for all |
| Controller Version and Capabilities | ||||
| CAPS | 64 |
0x040
|
R | SD and eMMC controller implementation definitions |
| VERSION | 16 |
0x05E
|
R | Controller version |
| Boot Timeout Counter | ||||
| BOOT_TIMEOUT_CNT | 16 |
0x070
|
RW | Program the boot timeout value counter |