Slave Interrupt Handler

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID: AM011
Release Date: 2023-10-05
Revision: 1.6 English

Table 1. I2C Slave Interrupt Handler
Task	Register	Register Field	Bits	Operation
Read interrupt status register	ISR, `0x10`	All	9:0	Read operation
Write the status back to clear the interrupts so no events are missed while processing this interrupt.
Write back interrupt status register	ISR, `0x10`	All	9:0	Clear bits detected as set
Get the enabled interrupts (imr)	IMR, `0x20`	All	9:0	Read operation
Use the mask register AND with the interrupt status register so disabled interrupts are not processed (~(imr) and IntrStatusReg). Data interrupt (if interrupt status register and data): Master wants to perform more data transfers. Check for completion of transfer; signal upper layer if done. For sending transmit FIFO fill (see Transmit FIFO Fill). Else receive slave data (see Slave Receive).