Linked-List Descriptor Use Case

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

Each descriptor is 256 bits wide, the first 128 bits store the descriptor information and the next 128 bits provide a pointer to the next descriptor. In this mode, the descriptor can be located anywhere in the memory (it might not be in the same 4K page).

  • Each descriptor is 256 bits wide.
  • Each descriptor must be 256-bit aligned.
  • The descriptor element type is always 1 (in link-list descriptor mode).
  • DMA channel can only fetch the next descriptor if it has read a current descriptor. Two descriptor fetches require two AXI reads.
Table 1. Buffer Descriptor Format in Linked-list Descriptor Mode
ADDR LSB [31:0] WORD0
RSVD [31:12] ADDR MSB [11:0] WORD1
RSVD [31:29] SIZE [29:0] WORD2
RSVD [31:5] CTRL [4:0] WORD3
NEXT DSCR ADDR LSB [31:0] WORD4
RSVD [31:12] NEXT DSCR ADDR MSB [11:0] WORD5
RSVD [31:0]   WORD6
RSVD [31:0]   WORD7