Processor Control and Status Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID: AM011
Release Date: 2023-10-05
Revision: 1.6 English

The following table provides an overview of the dual RPU system control and status registers (the RPU_DUAL_CSR register module).

Table 1. Dual RPU Control and Status Register Overview
Register Name	Offset Address	Access Type	Description
GLOBAL_CNTL	`0x000`	RW	Global control
GLOBAL_STATUS	`0x004`	R	Miscellaneous status information
ERROR_CNTL	`0x008`	RW	Error response enable/disable
CCF_VAL	`0x054`	RW	Common cause signal value
CCF_MASK	`0x024`	RW	Common cause signal mask
SAFETY_CHK	`0x0F0`	RW	Safety check register
RPU0_CONFIG RPU1_CONFIG	`0x100` `0x200`	RW	Configuration parameters
RPU0_STATUS RPU1_STATUS	`0x104` `0x204`	R	RPU status
RPU0_PWRDWN RPU1_PWRDWN	`0x108` `0x208`	RW	Power-down request from the CPU
RPU0_ISR , RPU1_ISR	`0x114`, `0x214`	WTC	Interrupt status
RPU0_IMR , RPU1_IMR	`0x118`, `0x218`	R	Interrupt mask
RPU0_IEN , RPU1_IER	`0x11C`, `0x21C`	W	Interrupt enable
RPU0_IDR , RPU1_IDR	`0x120`, `0x220`	W	Interrupt disable
RPU0_CACHE_BASE RPU1_CACHE_BASE	`0x124` `0x224`	RW	Destination base address
RPU0_AXI_OVERRIDE RPU1_AXI_OVERRIDE	`0x128` `0x228`	RW	RPU attribute override