Buffer Descriptor Format

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The buffer descriptor (BD) format used in scatter-gather mode is shown in the following table. Both the SRC and DST implement the same format descriptor with a few exceptions. Similar words are implemented in the control registers, which can be used in simple DMA mode. By dividing the descriptor into 32-bit words and implementing them on the control registers, a consistent view is provided in both simple and scatter-gather mode.

Table 1. Buffer Descriptor Format
Word Number Field Name Size (bytes) Bits Description
0 ADDR LSB 4 [31:0] Lower 32 bits of the address pointing to the data/payload buffer.
1 ADDR MSB 4 [11:0] Upper 12 bits of the address pointing to the data/payload buffer.
[31:12] Reserved.
2 SIZE 4 [29:0] Buffer size in bytes (1 G = 230 )
[31:30] Reserved.
3 CNTL 4 [0]

Coherency: Reserved
[1]

DSCR element type:

Each descriptor can be viewed as a 128/256-bit descriptor.

0: Current descriptor size is 128 bits (linear)

1: Current descriptor size is 256 bits (linked-list)
[2]

INTR

0: Completion interrupt is not required

1 (SRC-side): Interrupt is set at the completion of this element. Completion indicates that data is read, but it could be in the DMA buffer (and not yet written to destination).

1 (DST-side): Interrupt is set at the completion of this element. Completion indicates that data is written to the destination location and BRESP is received.
[4:3]

CMD

This field is valid only on a SRC descriptor and is reserved on a DST descriptor.

00: Next DSCR is valid, the DMA channel continues with scatter-gather operation (in this case). Software must ensure that the next descriptor is valid.

01: Pause after completing this descriptor. Software can use this command to pause the DMA operation and update the descriptors. After the software is done updating the descriptors, it can resume the channel from where it paused. If software has updated a descriptor to new location, it can resume the channel and tell it to fetch the descriptor from the new location. Pause mode allows software to keep the state of the channel and avoid the enable sequence.

10: STOP after completing this descriptor. After the DMA channel detects STOP, it finishes the current descriptor payload transfer and goes to IDLE. Any subsequent transfer requires the software to follow an enable sequence. STOP does not preserve the state of the channel.

11: Reserved.
[31:5] Reserved.
4 NEXT ADDR LSB 4 [31:0] Lower 32 bits of the NEXT descriptor address. This field exists only if the DSCR element type is set as 1.
5 NEXT ADDR MSB 4 [11:0] Upper 12 bits of the NEXT descriptor address.
[31:12]

Reserved.

This field exists only if the DSCR element type is set as 1.
6 Reserved 4 [31:0]

Reserved.

This field exists only if the DSCR element type is set as 1.
7 Reserved 4 [31:0]

Reserved.

This field exists only if the DSCR element type is set as 1.