I/O Peripheral Clock Frequency Requirements

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The following table lists the I/O peripheral clock frequency requirements and links to the clock section of the various controller chapters.

Table 1. I/O Peripheral Clock Frequency Requirements
Peripheral and Mode Description
CAN FD, see System Signals
  All Modes CAN_REF_CLK frequency must be less than the LPD_LSBUS_CLK (APB interface).
  Set to 160 MHz ±0.25% to satisfy the CAN FD spec.
GEM Ethernet, see GEM Clocks
  GEM_TX Set to 125 MHz ±100 ppm. This is governed by the 802.3 Ethernet specification and might limit the maximum operational frequency of the PLL selected.
SPI Controller, see SPI Clocks
  Manager Mode SPIx_REF_CLK >= 4 * LPD_LSBUS_CLK.
  Response Mode SPIx_REF_CLK >= 2 * LPD_LSBUS_CLK.
UART Controller, see UART Clocks

There is a restricting shown in the Baud Rate Divider section.