System Timestamp Counter Implementations

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The AMD Versal™ device includes a single system timestamp counter located in the LPD. It can be programmed and read using the secure SCNTRS register set and read-only using the SCNTR register set.

The AMD memory protection unit (XMPU) in the Versal adaptive SoC is similar to the one in the AMD Zynq™ UltraScale+™ MPSoC. The following table shows the functional differences.

Table 1. System Timestamp Counter Implementations
Device Generation Counter Name Error Handling Response to Address in Secure Range but ID Match Fails Dynamic Reconfiguration after Boot
UltraScale+ MPSoC SCNTRS Poison the base address Allow or deny based on default read/write configuration Not supported
Versal adaptive SoC SCNTR, SCNTRS Issue a fail message on the interconnect back to initiator By default, transaction is denied Supported