SD Commands

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The registers to generate SD commands are listed in the following table.

Table 1. SD Commands
Register SDMA Command ADMA Command CPU Data Transfer Non DAT Transfer
SDMA system address, argument 2 Yes/No No/Auto CMD23 No/Auto CMD23 No/No
Block size Yes Yes Yes No (protected)
Block count Yes Yes Yes No (protected)
Argument 2 Yes Yes Yes No (protected)
Transfer mode Yes Yes Yes No (protected)
Command Yes Yes Yes Yes

The table shows register settings for three transactions: SDMA generated transactions, ADMA generated transactions, and CPU data transfers and non-DAT transfers. When initiating transactions, the host driver programs these registers sequentially from 000h to 00Fh. The beginning register offset is calculated based on the type of transaction. The last written offset is always 00Fh because writing to the upper byte of the command register triggers the issuance of the SD command.

The command number is selected using command [cmdindex].

Table 2. SD Controller Commands
Command Description Response Related Registers
CMD17 Single block read  

blocksize [xfer_blocksize]

CMD18 Multi-block read    
CMD24 Single block write    
CMD25 Multi-block write    


CMD53 I/O read/write extended    
Auto CMD6      
Auto CMD12    


Auto CMD23    

sdmasysaddrlo [sdma_sysaddress]

Auto CMD41      
Auto CMD42      
Auto CMD51