Slave Receive Polled

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English
Table 1. I2C Slave Receive Polled
Task Register Register Field Bits Operation
Read status register Status, 0x04 All 8:0 Read operation
Read interrupt status register ISR, 0x10 All 9:0 Read operation
Write back interrupt status register ISR, 0x10 All 9:0 Clear bits detected as set
Read status register Status, 0x04 All 8:0 Read operation
Write back status register Status, 0x04 All 8:0 Write status
Read status register Status, 0x04 All 8:0 Read operation
Perform the following operations until all bytes received (Loop-1 started).
Perform the following operations as long as SR and RXDV = 0 (Loop-2 started).
Read status register Status, 0x04 All 8:0 Read operation
If (status register and (DATA | COMP) != 0) && (status register and RXDV ==0) && receive byte count >0) then it is a failure.
Write back interrupt status register ISR, 0x10 All 9:0 Clear bits detected as set
Loop-2 ended
Perform the following operations until status register and RXDV!= 0 and receive byte count!=0 (Loop-3 started).
Receive byte Data, 0x0C DATA 7:0 Read operation
Read status register Status, 0x04 All 8:0 Read operation
Loop-3 ended
Loop-1 ended