SD and eMMC Controller Implementations

MPSoC to Versal SoC SD_eMMC Controller Improvements

The combination SD v3.0 and eMMC v4.51 controller in the Versal adaptive SoC is similar to the controllers in the AMD Zynq™ UltraScale+™ MPSoC SoC.

Improvements and changes include the following:

• Enhanced DLL with new programming model
• DLL is used for all frequencies above 25 MHz
• Separate SD 0 and 1 register sets for the DLL TAP delays
• Maximum frequency with external level shifter bumped from 19 to 20 MHz
• Tuning count default value changed from 32 to 40
• SD_REF_CLK divider set = 0 results in a divide by 1

Implementation Summary Table

The following table summarizes the SoC generations and controller implementations.