The BootROM sets configuration registers that apply to each boot mode. For QSPI boot mode, the BootROM sets the registers to the initial values shown in the following table.
| Register Name | Base Address | Register Value | Description |
|---|---|---|---|
| QSPI_REF_CTRL | 0xF126_0118 |
0x0100_0B00
|
Select PPLL divided by 11 (DIVISOR), clock enabled |
| MIO_Bank0_Schmitt_En | 0xF106_010C |
0x0000_1FBF
|
Enable Schmitt on QSPI MIO pins |
| OSPI_AXI_Sel | 0xF106_0504 |
0x0000_0000
|
QSPI selected |
| MIO_Bank0_Tristate | 0xF106_0200 |
0x03FF_E040
|
Disable 3-state override on QSPI MIO pins |
| RST_QSPI | 0xF126_0300 |
0x0000_0000
|
QSPI RST not asserted |
| Mode | 0xF103_0144 |
0x0000_0001
|
Generic QSPI mode |
| GQSPI_Cfg | 0xF103_0100 |
0x8008_0008
|
QSPI_REF_CLK is divided by 4 (BAUD_RATE_DIV) |
| GQSPI_En | 0xF103_0114 |
0x0000_0001
|
Generic QSPI controller enabled |
| PMCPLL_CTRL | 0xF126_0040 |
0x0002_4800
|
PMC PLL (PPLL) setup uses reset defaults (REF_CLK multiplied by72 (FBDIV) and divided by 4 (CLKOUTDIV) |