Versal Adaptive SoC Technical Reference Manual (AM011) - Describes the hardware aspects of the AMD Versal™ Adaptive SoC, including the scalar engines in the processing system and the intelligent and adaptable engines in the programmable logic. - AM011
Document ID
AM011
Release Date
2026-03-06
Revision
1.9 English
Introduction
Introduction to Versal Adaptive SoCs
Device Introduction
Navigating Content by Design Process
SoC Hardware Overview
Features
Subsystems Overview
Block Diagram
Interconnect Features
System Performance Features
Software Programming
Software Environments
Embedded Microprocessor Code
Processor-to-processor Communications
Documentation
Technical Reference Manual Outline
Additional Documents
Hardware Architecture
Overview
Functional Unit Implementation Links
Chip-specific Content List
Device-level Interconnect Diagrams
Device-level Architecture
PS and PMC Interconnect Architecture
APU Subsystem
APU Interconnect Diagram
APU Functional Units
RPU Subsystem
RPU Interconnect Diagram
RPU Functional Units
PMC Subsystem
Platform Management and Control
Features
PMC-related TRM Sections
PMC Block Diagram
PMC Interconnect Diagram
PMC Interconnect Components
PMC Functional Units
PMC I/O Signals
NoC, DDRMC, PL Subsystems
NoC Interconnect
DDR Memory Controller
Programmable Logic
PL System Block Diagram
Configurable Logic Block
Digital Signal Processor
Block RAM
UltraRAM
Integrated Hardware Device Options
Hardware Accelerator
AI Engine
LDPC Decoder
CPM
CPM4 Module
CPM5 Module
CPM6 Module
Accelerator RAM and HBM Memory
Accelerator RAM
HBM Interface
PL High-speed Connectivity
100G Multirate Ethernet MAC
600G Channelized Multirate Ethernet
600G Interlaken with FEC
400G High-Speed Crypto Engine
Multistream Video Decoder Unit
Device I/O Connectivity
Device I/O Diagram
MIO and Dedicated I/O Banks
I/O Buffer Pin Banks
PL HDIO Banks
DDR Memory Controller I/O
Pipe Transceivers
Integrated Silicon
Encryption Disabled Devices
Package Integration
Monolithic SoC Die Layout Concept
SSI High-Bandwidth Memory Package Concept
SSI Multiple Super Logic Regions
Test and Debug
Platform Boot, Control, and Status
Overview
Platform Management Generational Comparisons
Versal Device PMC Compared to Previous Devices
Non-Secure Boot Flow
Secure Boot Flow
Asymmetric Hardware Root of Trust Secure Boot
Configuration Update
Configuration Update with Key Revocation
PPK Revocation
SPK Revocation
Revocation as a Tamper Penalty
Symmetric Hardware Root of Trust Secure Boot
Configuration Update
Configuration Update with Partition Revocation
Boot Image
PDI Size Estimation
Boot Header
Boot Modes and Interfaces
Primary Boot Interfaces Table
Boot Search Limit
MIO Boot Interfaces
MIO Boot Interface Pin Buffer Settings
Boot Interface Signals
Dedicated Boot Signals
JTAG Boot Mode
OSPI Flash Boot Mode
OSPI Flash Boot Sequences
OSPI Flash Boot Commands
OSPI Flash Device Interface
OSPI Flash Boot Register Settings
QSPI Flash Boot Mode
QSPI Flash Boot Sequences
QSPI Flash Boot Commands
QSPI Flash Boot Interface
QSPI Flash Boot Register Settings
SD Flash Boot Mode
SD Flash Boot Interface
SD Boot Register Settings
eMMC v4.51 Boot Mode
eMMC Boot Interface
eMMC1 Boot Register Settings
SelectMAP Boot Mode
SelectMAP Bus Width Detect Pattern Bit Order
SelectMAP Sequence
SelectMAP Boot Register Settings
SelectMAP Boot Mode Signals
Single Device Interface
Multiple Device Interface
Ganged Device Interface
SBI for JTAG and SelectMAP
Configuration Frame Unit
Configuration Frame Unit
Configuration Frame Interface
Platform Management
Functional Safety Management
Single Point Fault Detection
Common Cause Failure Detection
Latent Fault Detection
Isolation Features
Additional Features
Dynamic Function eXchange
Power Management
Power Modes
Security Management
Tamper Monitoring and Response
Secure Key Storage and Management
Key Selection
Battery-Backed RAM Key
eFUSE Key
Key Update Register
Boot Header Key
Storing Keys in Encrypted Form (Black)
Physically Unclonable Function
Key Management Summary
User Access to Hardware Cryptographic Accelerators
System Error Management
Platform Hardware Reference
Hardware Boot Events
Boot Header Register Initialization Feature
Device State After RCU BootROM
PL-PMC GPI and GPO Port Signals
Software Platform Service Requests
Power and Isolation Requests
Reset Service Requests
CoreSight Wake-Up Requests
Hardware Allocated to PLM Firmware
BootROM Error Code Table
Device Identification
Address Maps and Programming Interfaces
Address Maps
4 GB Processor System Address Map
16 TB NoC Interconnect Address Map
Address Map Perspectives
Programming and Configuration Interfaces
Programming and Configuation Interface List
APB and AXI Programming Interfaces
NPI Programming Interface
CFU Controller Programming Interface
Signals, Interfaces, Pins, and Controls
Dedicated Pins
Multiplexed I/O Signal Pins
MIO-at-a-Glance Tables
PMC MIO Pin Tables
LPD MIO Pin Table
MIO Routing Considerations
MIO-EMIO Interface Routing Options
MIO Pin Buffer Controls
Input Buffer Control Registers
Output Buffer Control Registers
MIO Pin Routing
MIO Routing Diagram
MIO Routing Control Registers
MIO Routing Functionality Details
MIO Pin Programming Example
PCIe Resets on MIO Pins
Processor and DMA Units
Application Processing Unit
Features
System Perspective
APU System Block Diagram
APU MPCore Functional Units
System Interfaces
Memory Space
Execution Pipelines
CPU Pipeline
FPU Pipeline
NEON Pipeline
Cryptography Engine
APU Address Model
Virtualization
Server Architecture
Processor Counters
Applications
Physical Counter
Virtual Counters
Private Counters
Programming
PS FPD Interrupts
Hardware Interrupts
GIC-500 Interrupt Controller
Exception Levels
Virtual Interrupts
Interrupt Translation Services
LPI and ITS Cache Updates
Register Reference
Processor Control and Status Registers
GIC Registers
Real-time Processing Unit
Features
Cortex-R5F Processor Implementation
System Perspective
Block Diagram
AXI System Interfaces
Operating Modes
Lock-Step Architecture
Configuration Registers
Power Modes and States
Address Maps
CPU Local and Global Memory Map
Memory Map Diagram
Processor Memory Datapaths
Tightly-coupled Memories
Memory Error Detection and Correction
RPU Memory Protection Unit
Interrupts
System Interrupts Generated by RPU
GIC Interrupt Controller
Block Diagram
Software Generated Interrupts
Shared Peripheral Interrupts
SPI Interrupt Sensitivity
Interrupt Prioritization
System Errors Generated by RPU
Test and Debug
Interrupt Injection Mechanism
Events and Performance Monitor Unit
Register Reference
Processor Control and Status Registers
LPD DMA Controller
Features
LPD DMA Implementations
System Perspective
Block Diagram
Functional Units
Common Buffer
System Interfaces
AXI Read Arbiter
AXI Write Arbiter
Memory Coherency
PL Flow Control Interface
Programming Guide
Channel Block Diagram
Modes and States
Simple Mode Programming
Sequence Steps
Descriptor Mode Programming
Data Flow
Model
Buffer Descriptor Format
Descriptor Format
Linked List Mode Use Case
Linear Descriptor Use Case
Linked-List Descriptor Use Case
Hybrid Descriptor Use Case
Buffer Descriptor Summary
Interrupt Handling
Done Interrupt Accounting
Over Fetch
Transaction Control
Outstanding Transactions
Rate Control
PL Flow-Control Interface
Flow-Control Interface Considerations
Flow-Control Programming Model
Attached to the SRC
Channel Reading from a Flow Controlling a PL Destination
Channel Writing to a Flow Controlling the PL Destination
Interrupts
Descriptions
Transaction Security
Channel Pause
Coming Out of Pause
Programming Model for Changing DMA Channel States
Channel Enabled
Channel Disabled
Register Reference
DMA Channel Registers
I/O Flow Control Signals
Embedded Processors and Security Units
Overview
RCU ROM Code Unit
Features
RCU Implementations
PPU MicroBlaze Processor
Features
PPU Implementations
Programming Model
Interrupts Associated with PPU
Errors Associated with PPU
Authenticated JTAG
Tamper Event Monitoring and Response System
PMC Register Reference
PMC Global Registers
PMC Local Registers
PMC DMA Units and Stream Switch
Overview
PMC DMA Features
PMC DMA Implementations
System Perspective
Block Diagram
Stream Switch Routes
Programming Interface
Interrupt Signal
Clock Signal
Reset Signal
AXI Stream Switch Interface Signals
Operations
SRC DMA Module Operation
DST DMA Module Operation
DMA Command FIFO
AXI FIXED Burst
Programming Considerations
PMC DMA Registers
Security Units
Overview
PMC AES
Secure Hash Algorithms
RSA/ECC
True Random Number Generator
Physically Unclonable Function
Battery-Backed RAM
PS Manager
Features
System Perspective
Interrupts
Reset
Processor State After Reset
Service Requests to PSM Firmware
Power Islands
Wake-Up Service Requests
PSM Register Reference
PSM Global Registers
PSM Local Registers
Interconnect
Overview
Features
Interconnect Implementations
FPD SMMU and Coherent Implementations
iPort and ePort Implementations
AXI Interconnect Implementations
AXI Switch Feature Implementations
UltraScale+ MPSoC versus Versal Adaptive SoC Comparisons
Memory Protection Unit Implementations
Peripheral Protection Unit Implementations
System Perspective
Network On Chip
PMC and PS Interconnect
Register Module Programming Interfaces
Detailed Interconnect Diagram
Interconnect Switch Diagrams
PMC Interconnect
PMC IOP Interconnect
PSM Interconnect
LPD and OCM Interconnect
LPD IOP Interconnect
FPD Interconnect
FPD Auxiliary Interconnect
PS CPM Interconnect
Interconnect Channels and Ports
Interconnect Register Set Overview
Transaction Hosts and Their Attributes
Transaction Hosts
Address
PMC and PS Perspectives
Address Generation
Data
System Management ID
Features
SMID Implementations
SMID Summary Table
TrustZone Security
Features
Architecture
Security Profiles
PL Security
TrustZone Profile
AxCACHE
Quality of Service
Traffic Types
QoS Signal Generation
Integrity Checks
Poisoned Transaction
Transaction Routes
Routing Notices for PMC
PMC DMA and GEM Interaction
System Memory Coherent Route
Routing and Coherency Controls
CPM Transaction Routes
System-level Routes
Routing Restrictions through CCI
NoC Path from PMC through to FPD and PL is Not Supported
Interconnect Switch Functionality
Switch Architecture
Conceptual Interconnect
Features
Switch Ingress Ports
iPort Protocol Integrity Checker
iPort Isolation
iPort Parity Unit
Switch Egress Ports
Interconnect ePort Timeout Units
ePort Reset
ePort Parity Unit
ePort Isolation
Interconnect Interface Protocols
PS Interfaces to/from the PL fabric
PS-to-PL AXI Fabric Interfaces
PL-to-PS AXI Fabric Interfaces
PL-to-PS ACE Interfaces
PL-to-PS ACP Interface
PL Address Translation
Shared Memory and Virtualizations
System Perspective
APU Virtualization
Interrupt Virtualization
System Memory Management Unit
Features
SMMU TBU Instances
Address Translation Examples
Native, Non-Virtual
Virtual
Stream IDs
Memory Protection Functionality
SMMU Register Reference
Cache Coherent Interconnect
Features
Comparison to Previous Generation Devices
Cache Coherency
Two-way Coherency
I/O Coherency
Snoop Filter
Snoop Filter Table Management
AXI Outgoing Ports
Striping NoC Interfaces
Transaction Attribute Management
QoS Response
CCI Register Reference
CCI CSR
CCI Core
Memory Space Protection
Types of Protection Units
TrustZone Security
Always-Secure Register Programming Interfaces
Use Case Example
Memory Protection Units
Features
XMPU Instances
Protection Operations
Error Handling
AXI Transaction Signals
Configuration
XMPU Register Reference
XMPU Register Set
XMPU Write Lock
Peripheral Protection Units
Features
XPPU Instances
System Perspective
Protected Addresses
Transaction Checking Operations
SMID Validation
SMID Register
Aperture Permission Checking
Permission and TrustZone Registers
Aperture Register Map
Errors
XPPU Register Reference
XPPU Register Set
XPPU Write Lockdown
Interrupts and Errors
System Interrupts
System Interrupt Controllers
Sensitivity
System Interrupts Table
System Interrupts
Register Reference
Interrupt Masking Registers
Inter-Processor Interrupts
Features
IPI Controller Implementations
System Perspective
IPI Agents
SMID Profiles
Agent Communications
Interrupt Architecture
Register Reference and Address Map
IPI Registers
Message Buffer
Message Passing Architecture
Programming Examples
Send an IPI Communication
Receive an IPI Communication
System Errors
Error Sources
Error Accumulator Modules
Error Management
Types of Errors Reference
System Error Summary Tables
System Errors to PMC EAM
System Errors to PSM EAM
EAM Register List
Timers, Counters, and RTC
Real-Time Clock
Features
Counter Module
Calibration
RTC Accuracy
External Clock Crystal and Circuitry
Interfaces and Signals
RTC Register Reference
System Timestamp
System Timestamp Counter Implementations
Triple-Timer Counters
Features
TTC Implementations
Block Diagram
Overflow Detection Functional Model
Interval Timing Functional Model
Event Timer Functional Model
TTC Register Reference
TTC I/O Interface
TTC I/O Diagram
TTC I/O Signals
System Watchdog Timers
Features
Window Timer Applications
SWDT Implementations
Watchdog Timer Instances
System Perspective
SWDT Block Diagram
Programming Interface
Watchdog Timer Clock Periods
Signals to the Timer
Signals Generated by the Timer
Window Watchdog Timer Mode
Windowed Waveform Diagram
Window Mode Features and Options
Windowed Basic Mode
Basic State Diagram
Basic Program Sequence Monitor
Basic Window Programming Sequence
Windowed Q&A Mode
Q&A State Diagram
Q&A Programming Sequence
Q&A Token Response Bits Table
Generic Watchdog Timer Mode
Generic Waveform Diagram
Generic Programming Sequence
Register Reference
Timer Register Set
System-Level Registers
SWDT I/O Interface
SWDT I/O Interface Signals
Memory Controllers, Integrated RAMs, and Storage Registers
Overview
DDR System Memory Controller
High-Bandwidth Memory Interface
Integrated RAM Memory
Flash Memory Controllers
PL-based RAM
Storage Registers
On-Chip Memory
OCM Features
OCM Memory Implementations
System Perspective
System-Level Block Diagram
States
OCM Address Locations
Memory Address Protection
ECC Protection
ECC Operations
Accelerator RAM
Features
Accelerator RAM Implementation
Interconnect and Block Diagram
System Signals
Programming Interface
Exclusive Access Monitors
Accelerator RAM Register Sets
I/O Peripheral Controllers
CAN FD Controller
Features
CAN/CANFD Controller Implementations
System Perspective
Block Diagram
Object Layer
Logical Link Layer
MAC Transfer Layer
System Interface
System Signals
I/O Interface
Programming Model
Modes and States
Reset State
Mode Table
Mode Transition
Configuration Mode
Normal Mode
Sleep Mode
Snoop (Bus Monitoring) Mode
Loopback Modes
Protocol Exception Event State
Bus-Off Recovery State
Configuration Sequence
Message Transmission
Cancellation
Message Reception
Acceptance Filters
RX Buffer Usages
Disabled RX Buffer
Enabled RX Buffer
Register Reference
Control and Status
Message Space Data
System-level Control Registers
CAN FD Controller I/O Signals
Gigabit Ethernet MAC
Features
GEM Interface Implementations
System Perspective
Block Diagram
Functional Units
System Signals
GEM Clocks
Controller Reset
System Interrupts
System Error
System Interfaces
I/O Interfaces
I/O Block Diagram
Clocks
Timestamp Unit Clock
Programming Model
Modes and States
10/100/1000 Operating Modes
Memory Packet Descriptors
Descriptor Length
DMA AXI Transactions
Burst Transactions
Transaction Routing and Coherency
Transmit Dataflow
Packet Buffer TX Functionality
TX Packets
TX Descriptor Entry Words
TX Descriptor Processing
MAC Transmitter
TX Broadcast Frames
TX Pause Frame
Quantum Time Base
Receive Dataflow
RX Packets
RX Packet Flow Monitoring
RX Descriptor Words
RX Descriptor Processing
MAC Receiver
Filtering
Hash Addressing
Capture All Frames
RX Broadcast Frames
VLAN Support
Wake-on-LAN Support
Magic Packet Events
Address Resolution Protocol
Specific Address 1 Filter Match
Multicast Hash Filter Match
Precision Timestamp Unit
MAC Pause Frames
RX Pause Frames
PFC Priority-based Pause Frame
Disable Copy of Pause Frames
Checksum Hardware
RX Checksum Offload
TX Checksum Offload
Register Reference
Control and Status
Statistics
System-Level Registers
AXI Transaction Control
GEM I/O Signal Reference
RGMII Interface Signals via MIO
GMII Interface Signals via EMIO
MDIO Interface Signals
Timestamp Unit Interface Signals
GPIO Controller
Features
GPIO Controller Implementations
System Perspective
Block Diagram
System Interface
System Signals
I/O Interface
Programming Model
Channel Block Diagram
Input Programming Model
Interrupt Programming Model
Output Programming Model
GPIO Registers
GPIO I/O Signals
MIO Signals
Assigned MIO Signals
EMIO Signals
I2C Controller
Features
I2C Controller Implementations
System Perspective
Block Diagram
APB Programming Interface
System Signals
Programming Model
I2C Interrupts
I2C Initiate Data Transfers
I2C Manager Read Using Polled Method
I2C Manager Read Using Interrupt Method
I2C Manager Write Using Interrupt Method
I2C Monitor Mode
I2C Programming Sequences
I2C Software Routines
Reset
Get Options
Check Bus is Busy
Transmit FIFO Fill
Send Byte
Reset Hardware
Setup Master
Master Send
Master Receive
Master Send Polled
Master Receive Polled
Enable Slave Monitor
Disable Slave Monitor
Master Send Data
Master Interrupt Handler
Setup Slave
Slave Send
Slave Receive
Slave Send Polled
Slave Receive Polled
Receive Data
Slave Interrupt Handler
Set and Clear Options
Set SCLK Frequency
Get SCLK Frequency
Self-Test
I2C Registers
I2C Control and Status Registers
Interface Routing Registers
System-level Clock and Reset Registers
I/O Interface Signals
LPD I2C Interface Signals
PMC I2C Interface Signals
SYSMON I2C Interface Signals
SPI Controller
Features
SPI Controller Implementation
System Perspective
Block Diagram
System Interface
System Signals
I/O Interface Overview
Programming Model Overview
Modes and States
Master Mode
Slave Mode
Data Loopback Mode
Functional Diagram
FIFOs
Data Transfer
SPI Registers
Controller Registers
System Level Registers
SPI Controller I/O Signals
UART Controller
Features
UART Controller Implementation
System Perspective
Block Diagram
System Signals
I/O Interface
Programming Model
Modes
UART Functionality
Block Diagram
Operations
System and Diagnostic Loopback Testing
Baud Rate Divider and Clock Dependencies
Transmit Character Frame
Hardware Flow Control
RTS Flow Control
CTS Flow Control
IrDA Functionality
Block Diagram
Transmit Encoder
Receive Decoder
Data Modulation
Interrupts
UART Registers
Controller Registers
SLCR Registers
Clock and Reset Registers
UART I/O Interface Signals
USB 2.0 Controller
Features
USB Controller Implementations
System Perspective
High-Level Block Diagram
System Interfaces
USB System Signals
Clocks
Controller Resets
System Interrupts
System Error Signal
I/O Interface
Power
Programming Model
Host Mode Data Structures
Register Reference
Controller Registers
XHCI Registers
Host Capabilities, Offset, and Operations Registers
Port Status, Control, Host Interrupter, Event Ring, and Doorbell Registers
Miscellaneous Control, Status, and Capabilities Registers
Miscellaneous Configuration, Control, and User Registers
Device and Command Registers
System-Level Registers
LPD System-Level Registers
PMC System-Level Registers
Clock and Reset Registers
USB I/O Interfaces
Port Indicator, Fault, and Power Select Signals
Flash Memory Controllers
Octal SPI Flash Memory Controller
Features
System Perspective
Block Diagram
Functional Units
System Interfaces
System Signals
I/O Interface
Programming Model
Access Modes
Memory Access Modes
Polling Feature
Start-up Sequences
Direct Access Mode
DMA Programming Model
DMA Features
Programming Steps
Source DMA
Destination DMA
Configuration Restrictions
Interrupts
Controller Interrupts
Register Reference
OSPI Controller Registers
OSPI SRC DMA Registers
OSPI DST DMA Registers
OSPI System-Level Registers
OSPI Flash Device Interface
OSPI Flash Interface Diagrams
OSPI Flash Interface Signals
Quad SPI Controller
Features
QSPI Controller Implementations
System Perspective
Block Diagram
Functionality
System Interfaces
System Signals
QSPI Clocks
QSPIx_CLK Loopback Feature
Controller Resets
System Interrupt
System Error
I/O Interface
Programming Model
Modes and States
Start-up
Reset
PIO Mode
DMA Mode
I/O Programming
Configurations
Clock Tap Control Settings
I/O Striping Function
Striping Programming Examples
Striping with Odd Byte Count
Command Words
Word Format
Immediate Data Field Usage
Programming
Programming Flowchart
DMA Data Transfer Length Examples
PIO Mode Programming Model
DMA Programming Model
Polling Programming Model
Register Reference
QSPI Controller Registers
QSPI System-Level Registers
QSPI Flash Device Interface
QSPI Flash Interface Diagrams
QSPI Flash Interface Signals
SD_eMMC Controller
Features
SD and eMMC Controller Implementations
System Perspective
Block Diagram
Functional Units
System Interfaces
System Signals
SD Clocks
Controller Reset
System Interrupts
System Errors
I/O Interfaces
Modes and States
Speed Modes
States
Main Functionality
Command Controller
Transmit Control Unit
Receive Control Unit
Timeout Control
Data Transfer Block Buffer
I/O Functionality
Card Detect
Voltage Level Shifter Interface
I/O Clock Functionality
Clock Block Diagram
Controller Clock Start-up
I/O Clocking Modes
I/O Clock Frequency Control Sequence
25 MHz I/O Clock Range
Low-speed Clock Control Settings
Clock Frequency Divider Register Settings
High-speed I/O Clocking
DLL Programming Model
High-speed Clock Control Settings
High-speed TX Clocking
High-Speed RX Clocking
Auto-tuning Unit in DLL
Manual DLL Programming Sequence
DLL Presets
DLL Programming Example
SD Commands
SD Command Response Registers
Register-driven DMA Mode
Descriptor-driven DMA Mode
Register Reference
System-Related Registers
Control and Status Registers
I/O Interface Control Registers
Command, DMA, and Data Registers
Interrupt and Status Registers
SD Flash Interfaces
SD Flash Interface v2.0 Diagram
SD Flash Interface v3.0 Diagram
SD Flash Interface Signals
eMMC Interface
eMMC v4.51 Flash Interface Diagram
eMMC Interface Signals
Clocks, Resets, and Power
Clocks
Clock Distribution
Clock Distribution Diagram
Cross-Domain Clock Routing Consideration
Clock Frequency Considerations
I/O Peripheral Clock Frequency Requirements
Flash Memory Controller Clock Frequency Requirements
Interconnect Clock Frequency Requirements
Device Source Clocks
Miscellaneous Device Clocks
PLL Clock Generators
Features
PLL Clock Generator Comparisons
PLL Clock Generator Instances
Block Diagram
PLL Integer Divide Helper Data
Reference Clock Frequency Dividers
Features
Block Diagram
Registers
PLL Clock Generator Registers
PMC Reference Clock Controls
LPD Reference Clock Controls
FPD Reference Clock Controls
Clock Monitor
Features
Base Time Period
Calculate Threshold Counts
Monitored Clocks
Clock Monitor Selection Summary
ClkMon Interrupts
Register Reference
ClkMon Registers
Resets
Features
Resets Comparisons
System Perspective
Reset Source Figures
Reset Circuitry, EAM, and JTAG TAP Controller
PMC Reset Controller
Reset Controllers
Programming Model
Reset Assertion Considerations
Reset Reason Register
Resets Overview
Device-Level Resets
Subsystem Resets
Debug Resets
POR_B Reset
Flowchart
System Integrity Monitoring Reset Sources
System Errors
System Monitoring Software
Reset Reference for Individual Blocks
PMC Block Resets
LPD Block Resets
FPD Block Resets
PL Resets
SoC Endpoint Resets
NPI Block Resets
NoC Resets
Persistent Registers
Global and Local
TrustZone Control
Power Control and Status
Clock and Reset Control
Miscellaneous Persistent Control Registers
Power
Power Diagram
Power Domains
Power Domain State Requirements
Power Islands
Test and Debug
Integrated Debug Overview
Integrated Debug Block Diagram
Debug Topics
Test and Debug Implementations
JTAG TAP Controller
Features
JTAG System Perspective
TAP Controller Instruction Availability
JTAG TAP Instructions
JTAG Register Reference
ERROR_STATUS Register
IDCODE Register
EXTENDED_IDCODE Register
DNA Register
JTAG_STATUS Register
JTAG Controller Interface Pins
Arm DAP Controller
Arm DAP Registers
Arm DAP Instructions
CoreSight Architecture
Funnels
Debug Data Flow Diagram through Funnels
Cross-Trigger Interface Architecture
Versal Device CTI Units
CTI Summary Table
FPD CTI Ports
LPD CTI Ports
Trace Port Interface Unit
Data Flow Diagrams
Output Interface
TPIU I/O Signals
CoreSight Register Reference
Debug Timestamp Counter
Debug Packet Controller
DPC Interfaces
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Arm Documents
Please Read: Important Legal Notices