System Interrupts

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

Each controller generates two system interrupts. The IRQ numbers refer to controllers 0 and 1, respectively.

  • Wake-up interrupt (IRQ# 158 and 160)
  • Controller interrupt managed by three sets of register controls (IRQ# 159 and 161)

The enabled controller interrupts are OR'd together and assert the SD/eMMCx system interrupt. The wake-up interrupt is separate from the controller interrupts. All system interrupts are listed in System Interrupts Table.