SWDT Implementations - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2025-03-11
Revision
1.7 English

The system watchdog timer (SWDT) helps to maintain a healthy and secure system by detecting errant software, deadlock conditions, tampering, and unexpected behavior.

The AMD Versal™ adaptive SoC SWDT includes a generic watchdog timer based on the MPSoC SWDT with the addition of a windowed environment mode that is derived from an AMD LogiCORE™ IP. The windowed mode also adds a Q&A token response handshake. The following table lists the SWDT implementations.

Table 1. SWDT Implementations
Device Generation Instances Window Feature MIO Signals
AMD UltraScale+™ MPSoC Three instances: CSU, LPD, FPD No  
Versal device Two instances: LPD_IOP, FPD

AMD version 0.08

Yes Clk, reset, pending, interrupt and gws signals