Intelligent Engines

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The Intelligent Engines include the AI Engine and the DSP Engine.

AI Engine

The AI Engine is a two-dimensional array of AI Engine tiles that each contain a high-performance VLIW vector (SIMD) processor, integrated memory, as well as interconnects for streaming, configuration, and debug. At the bottom of these tiles are the AI Engine array interface tiles that provide the necessary logic to connect the AI Engine to other resources including the PL, PS, and the NoC.

The AI Engine is integrated into the AMD Versalâ„¢ adaptive SoC AI Core series. For more information, see AI Engines and Their Applications (WP506) and for additional information, see the Versal Adaptive SoC AI Engine Architecture Manual (AM009).

DSP Engine

The DSP Engine combines high speed with small size to provide high performance and system design flexibility. The DSP Engines are integrated into the PL.

Each engine includes a dedicated 27 × 24 bit multiplier and a 58-bit accumulator. The multiplier can be dynamically bypassed, and two 58-bit inputs can feed a single-instruction multiple-data (SIMD) arithmetic unit (dual 24-bit or quad 12-bit add/subtract/accumulate), or a logic unit that can generate any one of ten different logic functions on the two operands.

New functional modes are implemented in the DSP Engine, including:

  • 18 x 18 + 58 two's complement MAC with back-to-back DSP Engines
  • Single-precision floating-point (binary32) accumulation
  • Three-element two's complement vector dot product with accumulate or post-add in INT8 mode

For more information, see the Versal Adaptive SoC DSP Engine Architecture Manual (AM004).