Interrupt and Status Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2023-10-05

Revision

1.6 English

The following table lists the interrupt and status registers for the SD_eMMC controller.

Note: These registers are defined with multiple data widths. However, all registers are accessed as 32-bit read/write transfers with addresses aligned on a 32-bit address boundary.

Table 1. SD_eMMC Interrupt and Status Registers
Register Name	Width		Access Type	Description
Slot Interrupts
SLOT_INTR_STS	16	`0x024`	R	Read the interrupt signal for each slot
Normal and Error Interrupts
NORM_INTR_STS NORM_INTR_EN NORM_INTR_SIG_EN	16	`0x030` `0x034` `0x038`	WTC, R RW, R RW, R	Normal interrupt status Normal interrupt status enable Normal interrupt status signal output enable
ERR_INTR_STS ERR_INTR_EN ERR_INTR_SIG_EN	16	`0x032` `0x036` `0x03A`	WTC RW RW, R	Error interrupt status Error interrupt status enable Error interrupt status signal output enable