Shared Peripheral Interrupts

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

A group of over 150 system interrupts from various modules can be routed to one or both of the CPUs or the PL. The interrupt controller manages the prioritization and reception of these interrupts for the CPUs. The system interrupts are listed in System Interrupts Table.

These system interrupts are routed to the shared peripheral interrupt (SPI) ports on the RPU general interrupt controller (GIC).