Revision History

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The following table shows the revision history for this document.

Section Revision Summary
10/05/2023 Version 1.6
Introduction
General updates. Reorganized section and revised content throughout.
SoC Hardware Overview chapter. Renamed from Device Overview. Revised extensively, added new sections, and restructured content.
Processing System Overview, Platform Management Controller, and Implementation Table Links. Added new chapters.
Hardware Architecture
General update. Reorganized section and revised content throughout.
High-level Interconnect Diagrams Renamed from System Interconnect Diagrams.
Processing System Architecture Renamed from PMC and PS Architectures.
DDR I/O Banks Added new section.
Platform Management Controller Architecture Added list of PMC phases and removed Documentation Links section.
PMC Interconnect Components Added new section.
PMC I/O Signals Revised to clarify pin information.
PMC-related TRM Sections Added new section.
Integrated Memory Added new section.
AI Engine Revised to include additional information for the AI Engine.
HBM Interface Removed memory access restriction section.
Programmable Logic Integrated Hardware Renamed from Adaptable Engines in PL and revised.
Digital Signal Processing Engine Added more detailed information on the DSP.
Package Integration Renamed from Integrated Silicon and revised.
SSI Multiple Super Logic Regions Added new section.
Platform Boot, Control, and Status
General updates. Reorganized section and revised content throughout.
Platform Management Generational Comparisons Renamed from AMD Versal™ Device Comparison to Previous Generation Devices. Moved Boot Mode Comparison table to Boot Mode Implementations.
Asymmetric Hardware Root of Trust Secure Boot Added PPK Instances section.
PPK Revocation Revised introductory sentence.
PDI Size Estimation Removed VC1352 and added VP1902.
Boot Header Added note to description for 0x70 offset.
Boot Modes and Interfaces Renamed from Boot Modes. Removed Boot Pin Usage Guide and Boot Mode Search Limits sections.
Primary Boot Interfaces Table, Boot Mode Implementations, Boot Search Limit, Boot Interface Signals, Dedicated Boot Signals, MIO Boot Interfaces, and MIO Boot Interface Pin Buffer Settings. Added new sections.
OSPI Flash Boot Sequences and OSPI Flash Device Interface Added new sections.
JTAG Boot Mode Reorganized content into sub-sections.
OSPI Flash Boot Mode Renamed from Octal SPI Boot Mode. Removed OSPI commands supported by RCU for boot table.
OSPI Flash Boot Commands Renamed from Octal SPI Signals, added new sub-sections, and removed OSPI Boot Mode Signals table.
QSPI Flash Boot Interface Renamed from Quad SPI Boot Mode. Reorganized section and revised content throughout.
SD Flash Boot Interface Added new section.
eMMC v4.51 Boot Mode Renamed from eMMC1 Boot Mode.
eMMC Boot Interface Added new section.
SelectMAP Boot Mode Signals Renamed from SelectMAP Signals and revised.
SelectMAP Bus Width Detect Pattern and Bit Order

Added JTAG_STATUS register reference for the SMAP bus detect width.

Hardware Allocated to RCU BootROM Code Removed this section.
Hardware Allocated to PLM Firmware Revised and added new sub-sections.
Address Maps and Programming Interfaces
Address Maps Revised and added firewall information.
Programming and Configuration Interfaces Renamed from Programming Interfaces and revised content.
Signals, Interfaces, Pins, and Controls
PMC Dedicated Pins Renamed from Power and PMC Dedicated Pins, removed Power Pins section, added note for REF_CLK, and added REF_CLK0 and REF_CLK1.
MIO-at-a-Glance Tables Added Boot Pin Table Shading section.
Engines
MicroBlaze Processor Instances Added new section.
Embedded Processor, Configuration, and Security Units
RCU Implementations Added new section.
PMC Global Registers Added additional items to the bulleted list.
SBI for JTAG and SelectMAP Removed secure from Secure Stream Switch and changed HSDP to DPC in figure, as well as changed HSDP to DPC in first paragraph.
PMC DMA Units and Stream Switch Renamed from Secure Stream Switch.
Overview, PMC DMA Features, System Perspective, Operations, Programming Considerations, and PMC DMA Registers Added new sections.
Interconnect
AXI Interconnect Implementations Renamed from Comparison to Previous Generation Devices.
Host Transaction Attributes Summary Table Added new section.
SMID Comparisons Renamed from Comparison to Previous Generation of Devices.
Interconnect ePort Timeout Units Renamed from ePort Timeout.
PS to PL Interfaces Revised FPD_AXI_PL, FPD_ADDR_PL, and LPD_AXI_PL in table.
FPD SMMU and Coherent Implementations Renamed from Comparison to Previous Generation Devices.
Types of Protection Units Added Secure Registers.
Always-Secure Register Programming Interfaces Added new section.
Features Added Error Detection.
XMPU Instances The XRAM architecture has four XMPUs associated with the four XRAM banks.
Xilinx Memory Protection Unit Reorganized and revised this chapter.
Memory Protection Unit Implementations Added new section.
XPPU Implementations Added new section.
System Interrupts and Errors
General updates. Renamed section from Interrupts and Errors.
Sensitivity Added PL interrupt pulse width information.
IPI Controller Implementations Changed name from Comparison to Previous Generation Devices.
System Errors Revised for better flow and consistency.
Error Sources, Error Management, Types of Errors Reference, System Error Summary Tables, and EAM Register List. Added new sections.
Error Accumulator Modules Revised for better flow and consistency.
System Errors to PMC EAM Renamed from PMC Error Status and added Error IDs used by the software.
System Errors to PSM EAM Renamed from PSM Error Status and added Error IDs used by the software.
Timers, Counters, and RTC
System Timestamp Counter Implementations Added new section.
Triple-Timer Counters Added information on wave output.
Block Diagram In figure, renumbered timers from 0,1, 2 to 1, 2, 3.
Register Reference Changed timer numbering from 0,1, 2 to 1, 2, 3.
TTC I/O Diagram Added new section.
SWDT Implementations Renamed from Comparison to Previous Generation Devices.
SWDT Block Diagram Added I/O Signals and Clock Selection sections.
Window Mode Features and Options Renamed from Features and Options.
SWDT I/O Interface Signals Revised table.
Memory Controllers, Integrated RAMs, and Storage Registers
General update. Renamed section from Memory. Reorganized section and revised content throughout.
DRAM System Memory Controller, PL-based RAM, and Storage Registers. Added new sections.
OCM Memory Implementations Renamed from Comparison to Previous Generation Devices.
OCM Address Locations Renamed from Address Map.
I/O Peripheral Controllers
General update. Reorganized section and revised content throughout.
CAN/CANFD Controller Implementations, GEM Interface Implementations, GPIO Controller Implementations, I2C Controller Implementations, SPI Controller Implementation, UART Controller Implementation, and USB Controller Implementations. Renamed from Comparison to Previous Generation Devices.
System Signals Consolidated sub-sections into one section.
Block Diagram Removed device-dependent IRQ numbers from figure.
System Interfaces Consolidated sub-sections into one section.
RMII and RGMII Interface Signals via MIO Updated to match MIO-at-a-Glance table.
Timestamp Unit Interface Signals Added gem_tsu_ms information.
Output Programming Model Revised DIRM description.
GPIO Register Descriptions Revised I/O Buffer Control section.
APB Programming Interface Renamed from System Interface.
I/O Interface Signals Reorganized and revised table.
Flash Memory Controllers
OSPI Flash Interface Diagrams Added new section.
OSPI Controller Implementations, QSPI Controller Implementations, and SD and eMMC Controller Implementations. Renamed from Comparison to Previous Generation Devices.
OSPI Flash Interface Signals Added new section.
QSPI Flash Device Interface Renamed from QSPI I/O Interface.
QSPI Flash Interface Diagrams Renamed from Wiring Diagrams and revised.
QSPI Flash Interface Signals Renamed from QSPI MIO Signal Table and revised.
SD_eMMC Controller Renamed from SD 4.51 Controller and revised.
SD Flash Interfaces and eMMC Interface. Added new sections.
Clocks, Resets, and Power
Clocks Added note for PMC and PS clocks.
PMC Source Clocks Added note for REF_CLK device pin input.
Features Added new section.
Clock Monitor Selection Summary Added new section.
Resets Comparisons Renamed from Comparison to Previous Generation Devices.
Power Pins Added new section.
Test and Debug
Test and Debug Implementations Added new section.
JTAG TAP Instructions Revised instruction descriptions in the JTAG TAP instructions table.
12/16/2022 Version 1.5
Introduction
SoC Block Diagram Added AI Engine to block diagram.
Devices with Encryption Enabled Added new section.
Additional Documents Changed section name for CPM4 product guides. Added AI Engine.
Hardware Architecture
AI Engine Added information on AI Engine generations.
Package Integration Renamed from Silicon Integrated into Package and revised.
Platform Boot, Control, and Status
Boot Image Added AMD Vivado™ PDI verify information.
SelectMAP Bus Width Detect Pattern and Bit Order Revised SelectMAP Bit Order table.
SelectMAP Sequence Added additional boot and waveform information, including revising waveform figure.
Multiple Device Interface Updated connections in figure.
I/O Signals Added paragraph following the table.
Address Maps and Programming Interfaces
16 TB Address Map, 4 GB Processor System Address Map, and 4 GB Address Map by Name

Updated and aligned destination names.

Programming and Configuration Interfaces Renamed from Register Programming Interfaces.
Programming Interfaces Listed by Block/Subsystem Renamed from List of Programming Interfaces by Block and revised.
NPI Register Modules Removed NPI Register Modules table.
Signals, Interfaces, Pins, and Controls
Power Pins Revised descriptions for I/O Connectivity pins.
Embedded Processor, Configuration, and Security Units
Authenticated JTAG Changed PMC MicroBlaze™ to PPU MicroBlaze Processor and IF to Interface in figure.
PMC AES-GCM, PMC SHA3-384, and PMC RSA/ECDSA Added note for ED devices.
Interconnect
General updates. Reorganized and revised content.
Transaction Hosts Added new chapter.
Interface Types Added new chapter.
Interconnect ePort Timeout Units Added ePort time out, PMC_IRO_CLK, interrupt propagation, frequency scaling note, and timeout instances information.
XMPU Instances Renamed from XRAM and DDRMC Instances and revised.
Interrupts and Errors
Sensitivity Added new section.
Processor Errors Revised system errors.
Timers, Counters, and RTC
SWDT Block Diagram Revised note and added Interrupt and Error Signals section.
Programming Interface Removed LPD SWDT and FPD SWDT information.
Signal Descriptions Removed section.
Signals to the Timer Renamed from Reference Clock Signal and revised.
Signals Generated by the Timer Renamed from Timer Signals to System, MIO, and EMIO and revised.
SWDT I/O Interface Signals Renamed from SWDT I/O Signals and revised.
I/O Peripheral Controllers
I/O Block Diagram Deleted GMII/MII Interface and added GEMn_REF_SRC_SEL.
Block Diagram Added Regs to block diagram.
I2C Controller Deleted bulleted list and note.
I2C Controller Implementations Added AMD Zynq™ AMD UltraScale™ /AMD Versal™ adaptive SoC comparison information.
I2 Core Functionality Added new chapter.
System Interfaces Revised AXI DMA Master section.
EMIO Signals Added GPIO PL EMIO Signals table.
Test and Debug
Integrated Debug Overview Reorganized and revised content.
04/26/2022 Version 1.4
General updates. Revised the Address Maps chapter for better flow and consistency. Improved introduction and added content to the Inter-Processor Interrupts chapter. Added a section on CoreSight™ trace interface units. Revised the IP revision table for future expansion, changed the definition of CFU programming interface, updated the PDI estimation tables for Versal adaptive SoC series updates, and enhanced various sections with new links.
Introduction
Introduction to Versal Adaptive SoCs Added Versal HBM series.
Navigating Content by Design Process Reorganized chapter and revised content throughout.
SoC Hardware Overview Reorganized chapter and revised content throughout.
Documentation Reorganized chapter and revised content throughout.
Hardware Architecture
Hardware Architecture Reorganized entire section and revised content throughout.
Platform Boot, Control, and Status
Boot Image Revised introductory section to include information on the PDI image stored in supported Quad SPI, Octal SPI, and eMMC non-volatile memory devices. Revised Boot Image Block Diagram.
PDI Size Estimation Added AMD Versal™ AI Edge, Versal HBM, and AMD Versal™ Premium to the PDI estimation tables.
Boot Modes and Interfaces Revised Boot Image - Programmable Device Image section to include PDI size estimation. Revised eMMC1 in loh1519166448713.html#loh1519166448713__table_ft2_tws_5mb. Added information on search limit response.
QSPI Flash Boot Mode Revised 4-bit I/O Detection and 8-bit I/O Detection sections.
Power Management Updated low-power and system power domain descriptions in the Primary Power Domains table.
Address Maps and Programming Interfaces
Address Maps Reorganized chapter and revised content throughout.
Power Pins Reorganized and added subsections.
CFU Programming Interface Changed name from CFP Programming Interface Introduction and updated.
Signals, Interfaces, Pins, and Controls
Power Pins Updated Power Design Tools section.
PMC MIO Pin Table Updated Signal Route Control and MIO Pin Assignments By Banks sections.
Engines
Inter-processor Interrupts Added new section.
Interconnect
Interconnect ePort Timeout Units Added timeout programming sequence example.
PL Security Added new section.
TrustZone Profile Updated table.
OSPI Direct Access by PMC DMA via CCI Added new section.
SMMU TBU Instances Updated table.
Interrupts and Errors
Inter-Processor Interrupts Added Message Passing section.
SMID Profiles Added new section.
IPI Agents Added new section.
Flash Memory Controllers
Access Modes Added note.
SD Clocks Expanded and consolidated this section.
Memory Access Modes Revised Direct Mode section.
I/O Clock Functionality Changed name from Clock Functionality and revised entire section.
Register-driven DMA Mode Renamed from DMA Programming Model, reorganized, and revised.
System-Related Registers Added new section.
Control and Status Registers Added new section.
Clocks, Resets, and Power
PMC Block Resets Revised content in table for RCU, PPU, PMC DMA controllers, SBI boot interface module, and I/O peripherals
Test and Debug
CoreSight Architecture Revised chapter introduction.
Funnels Added new section.
Cross-Trigger Interface Architecture Added new section.
Data Flow Diagrams Renamed from TPIU I/O Data Flow Block Diagram and updated figure.
10/27/2021 Version 1.3
Introduction
SoC Hardware Overview Added high-bandwidth memory (HBM) and general updates.
Software Environments Changed name from System Software and revised throughout.
Data Packets Added new section.
PL Building Blocks Changed name from RPU and APU Multiprocessor Cores. Revised introductory paragraph and table.
Documentation Added new chapter.
Additional Documents Added Coherent PCIe Modules, AC/DC Data Sheets, and PCB Design Guide sections.
Documentation Navigator Added new section.
Hardware Architecture
High-level Interconnect Diagrams Added AXI SmartConnect core information.
Embedded Memory Added subsections.
High-Bandwidth Memory Interface Added new section.
Multistream Video Decoder Unit Added new section.
Integrated Hardware Options Added high-bandwidth memory interface to table.
AI Engine Added AI Engine Machine Learning section.
Package Integration Added new section.
Programmable Logic Overview Added I/O information.
Device I/O Connectivity Revised PL XPIO bank description.
Platform Management Controller Architecture Changed name from Platform Management Controller and general updates.
PMC Interconnect Diagram Changed name from PMC Interconnect.
I/O Buffer Pin Banks Added new section.
XPipe GTY Transceiver Use Cases Changed name from CPM4 Design, removed use cases 8 and 9, and renumbered use cases.
CPipe GTYP Transceivers Added new section.
DDR I/O Banks Added information on PL accessibility to XPIO banks on the left and right southern corners of the die.
Platform Boot, Control, and Status
Overview Added Platform Hardware Reference section.
Secure Boot Flow Added PLM runtime configuration registers area (RTCA) information.
JTAG Boot Mode Added BootROM Register Initialization for JTAG table.
PDI Size Estimation Added devices and updated PDI estimates.
Boot Modes and Interfaces Reorganized chapter and revised content throughout.
QSPI Flash Boot Mode Added QSPI32 data width 8 to Quad SPI Commands Supported by the RCU table.
QSPI Flash Boot Register Settings Added new section.
SD Boot Register Settings Added new section.
eMMC1 Boot Register Settings Added new section.
OSPI Flash Boot Register Settings Added new section.
SelectMAP Boot Register Settings Added new section.
Device State After RCU BootROM Added real-time configuration area information.
BootROM Error Code Table Clarified BootROM error information in the paragraphs before the table.
PMC and PS System Error Management Added new section.
Platform Hardware Reference Added new chapter.
Address Maps and Programming Interfaces
Versal Global Address Map Revised Global Address Map table.
4 GB Processor System Address Map Added RTCA location in PMC RAM.
4 GB Address Map by Name Added RTCA location in PMC RAM.
APB, AXI Programming Interfaces Added note recommendation.
Signals, Interfaces, Pins, and Controls
Power Pins Added recommendation to tie VCC_BATT and VCC_FUSE to ground when not used.
Engines
Memory Map Diagram Revised Local Address Space at 0xF900_0000 section.
PS FPD Interrupts Reorganized and changed subsection names.
GIC-500 Interrupt Controller Added Local Address Space at 0xF900_0000 section.
GIC Registers Added introductory paragraph.
Embedded Processor, Configuration, and Security Units
PMC Global Registers Added PL-PS Signals
PMC AES-GCM Added Galois Message Authentication Code and authenticated data (AAD) information.
Security Units Added new chapter.
Interconnect
AXI Interconnect Switches Changed name from Interconnect Switches.
Architecture Revised TEE definition in first paragraph and added information on enhanced hardware isolation.
Protection Operations Added new section.
XMPU Register Reference Added new section.
Xilinx Peripheral Protection Unit Reorganized chapter, changed subsection names, and revised content throughout.
Interrupts and Errors
System Interrupts Table Updated SWDT names.
IPI Controller Implementations Added system management ID (SMID) registers.
System Perspective Added introductory paragraph, revised System Management IDs, and added Access Protection
Interrupt Signal Mapping Added Observation Register information.
Error Accumulator Modules Revised, including adding System Error Accumulator Modules figure.
Types of Errors Reference Added new section.
Memory Errors Added new section.
Interconnect Errors Added new section.
Processor Errors Added new section.
System Watchdog Timer Errors Added new section.
System Software Errors Added new section.
Timers, Counters, and RTC
System Watchdog Timers Reorganized, renamed, revised, and added sections throughout this chapter.
SWDT Block Diagram Revised figure.
Reference Clock Signal Added EMIO signal names.
SWDT I/O Interface Signals Updated signal names.
Memory
Overview Added high-bandwidth memory.
Battery-Backed RAM Added new chapter.
Register Reference Added new section.
Flash Memory Controllers Added High-Bandwidth Memory Controllers section.
Small Storage Elements Added Processor Caches section.
PL Memory Building Blocks Added new section.
I/O Peripheral Controllers
CAN FD Clocks Changed name from Reference Clock and moved clock frequency restrictions to the Clocks chapter.
GEM Clocks Changed name from System Clocks and added GEM_TX section.
SPI Clocks Changed name from Reference Clock, added I/O SCLK Clock, and APB Programming Interface Clock sections.
UART Clocks Changed name from Reference Clock.
Flash Memory Controllers
QSPI Clocks Changed name from Clocks and added QSPIx_CLK Loopback Feature section.
Immediate Data Field Usage Added new section.
QSPI Flash Interface Diagrams Removed single 4-bit device on upper interface and dual-stacked 4-bit on upper clocks and data I/O interfacing options.
Low-speed Clock Control Settings Added Programming Sequence section and added Clock Status to table.
Clocks, Resets, and Power
Clock Frequency Considerations Changed section names and reorganized content.
Flash Memory Controller Clock Frequency Requirements Changed name from Flash Controller Clock Restrictions and reorganized content in table.
Interconnect Clock Frequency Requirements Changed name from Interconnect Clock Restrictions and added Low-speed Bus Clocks section.
PLL Clock Generator Registers Changed name from Clock Generators.
Test and Debug
Integrated Debug Block Diagram Changed name from System Architecture, added note, and revised PMC in the figure.
Data Flow Diagrams Added new section.
Debug Timestamp Counter Added new section.
06/29/2021 Version 1.2
General update. Added link to the security lounge where applicable.
Introduction
Embedded Processors Revised introductory paragraph.
Processing System Changed name from Device Implementation and moved from Hardware Architecture section.
Subsystems Added additional product names.
Additional Documents Added integrated hardware, PL memory and building blocks, and I/O buffers documentation.
Hardware Architecture
Figure 1 Updated PS-PL interface names. Moved GIC to another switch. Added FPD Aux and APB switches and added CPM-PS switch names.
System Memory Management Unit Removed TBU function information.
PMC Interconnect Diagram Organized functional units into groups.
Device I/O Connectivity Revised table.
Device-Level Diagram Added GTYP transceiver.
GTY and GTYP Pipe Transceivers Clarified the naming for the GTY and GTYP transceivers. Reorganized, revised, and added notes.
Device Implementation chapter Moved to Introduction section.
XPipe GTY Transceiver Use Cases Added new section.
Subsystems Revised version information for USB 2.0 controller.
Platform Boot, Control, and Status
PDI Size Estimation Added AMD Versal™ Premium devices.
Boot Header Added 0x38 and 0x58 to table. Revised 0x20, 0x128, and 0xF30 description.
Boot Modes and Interfaces Revised QSPI32 description.
QSPI Flash Boot Interface Revised QSPI_LPBK_CLK description.
BootROM Error Code Table Revised introduction. Added 0x35D-0x363, 0x108, 0x109, 0x11C, 0x11D, 0x11E, and 0x33E error codes. Revised description for 0x206, 0x207, 0x209, and 0x31E error codes.
Security Management Added link to UG1508 and to the design security lounge.
Secure Key Storage and Management Removed key selections column from the key sources table and removed decode values. Added link to AM018 and to the design security lounge.
Key Selection Added link to AM018 and to the design security lounge.
Physically Unclonable Function Added information on nominal VCC_PMC value.
Key Management Summary Updated key management summary table.
User Access to Hardware Cryptographic Accelerators Added Arm® v8 Cryptography Extensions in the APU MPCore.
Address Maps and Programming Interfaces
Versal Global Address Map Corrected destination names. Added NOC_AXI_PL_H and NOC_AXI_PL_L.
Address Maps Reorganized and changed subsection names.
4 GB Processor System Address Map Updated table.
4 GB Address Map by Name Updated table.
APB, AXI Programming Interfaces Added Secure Register Modules.
NPI Programming Interface Revised list of Features, Errors and Interrupts, and Access sections.
Signals, Interfaces, Pins, and Controls
Multiplexed I/O Signals and Pins Reorganized this chapter and changed some section names. Revised introductory paragraph.
PMC MIO Pin Table PMC MIO pin 21 routing corrected for FPD_SWDT (goes to RST_PEND). Added GEM to TSU clock name.
MIO Routing Considerations Changed name from I/O Pinout Considerations. Removed output enable and pull up/pull down information.
MIO Pin Buffer Controls Added new section.
Input Buffer Control Registers Changed name from Input Controls. Revised introductory paragraph and table.
Output Buffer Control Registers Changed name from Output Controls. Revised introductory paragraph.
MIO Routing Control Registers Added new section.
MIO Pin Routing Added new section.
MIO Routing Diagram Added new section.
MIO Routing Control Registers Added new section.
MIO Routing Functionality Details Added new section.
MIO Pin Programming Example Changed name from Pin Programming Examples.
IOP SLCR Registers for PMC and LPD Removed chapter.
Engines
Power Modes and States Added Power Islands section.
CPU Local and Global Memory Map Changed name from CPU Local Memory Maps. Global map for lock-step mode added to table.
Memory Map Diagram Removed global address map view from figure.
Tightly-coupled Memories Revised to specify that 256 KB TCM is available in lock-step mode.
LPD DMA Controller Changed name from LPD DMA. Reorganized chapter and changed some section names.
Block Diagram Clarified eight independent channels, moved common buffer outside of sets of channels, revised to show registers are the individual terms, and added legend.
LPD DMA Implementations Revised first paragraph to include information on 4 KB common buffer and FCI. Added note specifying that the LPD DMA is a PS DMA controller that is also known as the ADMA.
APU System Block Diagram Updated PS-PL channel representations, moved TBU6 to PL, and updated interface names to/from PL.
Memory Coherency Added new section.
PL Flow-Control Interface General updates and added note.
Interrupts Added new section.
Embedded Processor, Configuration, and Security Units
Platform Processing Unit Reorganized this chapter and changed some section names. Specified that the PPU implements the MicroBlaze™ architecture and is a host on the PMC main switch.
Authenticated JTAG Revised description, and added link to UG1508 and design security lounge.
PMC Global Registers Revised descriptions for GLOBAL_GEN_STORAGE and PERS_GLOB_GEN_STORAGE registers.
PMC Local Registers Added new section.
PSM Register Reference Added new section.
Configuration Frame Unit Added information about decompression done in the CFU and compression default PDI setting.
Interconnect
General updates. Renamed chapters and reorganized content throughout.
AXI Interconnect Switches Changed name from Interconnect Hardware. Reorganized and revised content throughout this chapter.
Transaction Attributes Changed name from AXI Transaction Attributes. Reorganized and revised content throughout this chapter.
Transaction Routes Added new chapter.
AXI Interface Added new section.
PS to PL Interfaces Added note.
Register Reference Added new section.
Shared Virtual Memory Changed name from Memory Virtualization.
Features Added new section.
Cache Coherent Interconnect Reorganized and revised content throughout this chapter.
Timers, Counters, and RTC
System-Level Registers Added new section.
I/O Peripheral Controllers
System Signals Reorganized and revised.
Flash Memory Controllers
OSPI System-Level Registers Revised OSPI_IP_AXI_Sel description.
OSPI Clocks Revised clock description.
QSPI Clocks Revised clock description.
Clock Tap Control Settings Added second footnote to table.
SD_eMMC Controller Changed ADMA2 to ADMA throughout.
I/O Interface Control Registers Revised table.
Clocks, Resets, and Power
Clocks Added clock register modules information.
Clock Frequency Considerations Added new section.
Base Time Period Clarified REF_CLK and PMC_IRO_CLK frequencies.
Resets Reorganized, extensively revised, and added new content throughout this chapter.
Test and Debug
General updates. Reorganized throughout and renamed some sections.
Integrated Debug Overview Added new section.
JTAG Register Reference Revised SYSTEM_RESET JTAG register description.
JTAG TAP Instructions Alphabetized instruction names in table.
Integrated Debug Block Diagram Changed name from High-Speed Debug Port. Revised figure: swapped TAP and DAP, added TDI and TDO, clarified destinations, clarified 1-bit connection to GTY, and minor name improvements.
DPC Interfaces Added new section.
Debug Packet Controller Revised and added two subsections.
Additional Resources and Legal Notices
References Updated list of AMD references and added Cache Coherent Interconnect references.
Arm Documents Added additional Arm documents.
11/30/2020 Version 1.1
General updates.

Revised nomenclature for CPM to adhere to the PCIe® trademark. Changed Encrypt Only (EO) terminology to Symmetric Hardware Root of Trust (S-HWRoT), and Hardware Root of Trust (HWRoT) to Asymmetric Hardware Root of Trust (A-HWRoT). Changed the name of the secure debug feature to authenticated JTAG.

Introduction
General updates. Renamed chapters and reorganized content throughout.
Figure 1: System Processors Block Diagram Added system block diagram.
Processing System Changed name from Versal Device Variations, added Processing System Support Hardware, Integrated Hardware Options, and Comparison to Previous Generation AMD Devices.
Hardware Architecture
High-level Interconnect Diagrams Reorganized sections.
Integrated Hardware Added section.
Monolithic SoC Die Layout Concept Updated to clarify the layout as an example.
FPD Interconnect Diagram Removed APU Interconnect section.
PMC Block Diagram

Corrected and clarified MIO pin connections.

Boot Mode Implementations Changed secure debug to authenticated JTAG.
Device I/O Connectivity Added debug paths to this chapter.
Figure 1 Revised XPIPE area and enhanced the PSIO and EMIO representation.
MIO and Dedicated I/O Banks Added section.
GTY and GTYP Pipe Transceivers Added section.
Figure 1 Revised the CPM block and removed performance monitor.
Figure 1 and Figure 1 Removed performance monitor.
DDR I/O Banks Revised for clarity and renamed from DDR XPIO transceiver banks.
Platform Boot, Control, and Status
Secure Boot Flow Changed secure debug to authenticated JTAG.
Boot Image Revised chapter name, added information for the programmable device image, and clarified the figure.
PDI Size Estimation Added new section.
Boot Modes and Interfaces Updated QSPI entry in primary boot modes table, added the visual boot pin usage guide table, and added eMMC1 (raw) information to the boot mode search limit table.
QSPI Flash Boot Interface Added details for BootROM MIO setup.
SD Flash Boot Interface Revised the descriptions of WP, DETECT, and bus power. Added details for BootROM MIO setup.
SD2.0 Interface Specified WP, DETECT, and BUSPWR signals are optional. Added external voltage level translator information and added note to figure.
SD Flash Interfaces Specified WP, DETECT, and BUSPWR signals are optional. Added external voltage level translator information and added note to figure.
eMMC v4.51 Boot Mode Added information on the raw partition support for boot.
Table 1 Revised description for 0x301, 0x302, 0x31D, 0x320, 0x517, 0x518, 0x51A, and 0x51B error codes.
QSPI Flash Boot Sequences Added new section.
SelectMAP Boot Mode Added SelectMAP wait time and recommendation for JTAG during early phases and debug.
eMMC Boot Interface Added details for BootROM MIO setup.
SelectMAP Boot Mode Signals Added details for BootROM MIO setup.
OSPI Flash Boot Commands Added details for BootROM MIO setup.
BootROM Error Code Table Revised error codes and added new error codes.
Address Maps and Programming Interfaces
Address Maps Added new section and updated address maps.
IOP SLCR Registers for PMC and LPD Added new chapter.
NPI Programming Interface Clarified introductory paragraph.
Signals, Interfaces, and Pins
Power and PMC Dedicated Pins Combined Power Pins chapter with PMC Dedicated Pins chapter.
PMC Dedicated Pins Removed DXP/DXN pins from the table.
Power Pins Reorganized power pins table.
Engines  
Operating Modes Renamed from Operating States and clarified information.
Configuration Registers Renamed from Hardware Configuration and revised descriptions.
Power Modes and States Renamed from Power Modes.
CPU Local and Global Memory Map Clarified lock-step cache entries.
Memory Map Diagram Clarified 0xF900_0000 address information.
APU System Block Diagram Renamed from Block Diagram.
APU MPCore Functional Units Renamed from Functional Units.
Embedded Processor, Configuration, and Security Units
Embedded Processor, Configuration, and Security Units Renamed from Platform Processor, Configuration, and Security Units, as well as reorganized chapter content.
PMC Global Register Set Completed register descriptions.
Clock Monitor Added this chapter.
Interconnect
Overview Extensive additions and revisions throughout this chapter.
List of Interconnect Diagrams Added new section.
LPD Interconnect Port Diagram Added new section.
AXI Interconnect Switches Added new chapter.
Interconnect Switch Functionality Removed performance module probe.
Figure 1 Significant updates, including added new pathways, as well as added and removed transaction hosts.
Transaction Routing Added Transaction Routing Options Through CCI table.
Striping NoC Interfaces Added new section.
XPPU Instances Removed base address information.
Address Map Added new section.
Interrupts and Errors
System Errors to PMC EAM Added SSI technology to table.
PMC and PS System Error Management Added new chapter.
Timers, Counters, and RTC
Table 1 Added address offset and access type, as well as clarified content.
I/O Peripheral Controllers
Control and Status Revised register names.
Message Space Data Revised register names.
Modes and States Revised modes and options.
Programming Model Added two functional anomalies.
GPIO Controller Implementations Clarified device comparison.
I2C Interrupts Added new chapter.
Flash Memory Controller
Start-up Sequences Clarified idle status bit section.
Voltage Level Shifter Interface Added note and added bus power to figure.
Figure 1 Revised figure to add bus power.
SD Command Response Registers Added new section.
Clocks, Resets, and Power
Resets Extensive additions and updates throughout this chapter.
Table 2 Added footnote.
Test and Debug
Figure 1 Changed HSDP Link Layer Options to DPC Link Layer Options. Added HSDP to CPM PCIe® and Aurora (Hard IP).
TAP Controller Instruction Availability Added information on JTAG interface protections.
JTAG Register Reference Added to the JTAG_CONFIG register description.
JTAG TAP Instructions Changed SEC_DBG to AUTH_JTAG and updated description. Updated STATUS to JTAG_STATUS.
CoreSight Architecture Added more information for bandwidth calculations and reorganized content.
Arm DAP Controller Added link to Arm® Debug Interface Architecture Specification.
DPC Interfaces Removed reserved from the PCIe connector. Added HSDP to Aurora and PCIe connections and added debug host to PCIe connection. Added DPC link layer options table.
Debug Packet Controller Clarified HSDP defined protocol and added non-HSDP link layer information.
CoreSight Register Reference Added new section.
07/16/2020 Version 1.0
Initial release. N/A