Digital Signal Processing Engine

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The DSP engine combines high speed with a small footprint to provide high performance and system design flexibility. The DSP engines are integrated into the PL. The DSP engines have many applications beyond digital signal processing such as wide dynamic bus shifters, memory address generators, wide bus multiplexers, and memory-mapped I/O registers. The DSP engine is instantiated using the AMD DSP58 primitive. The number of DSP engines in a device varies. The counts are listed in the Versal Architecture and Product Data Sheet: Overview (DS950).

Each engine includes a dedicated 27 × 24 bit multiplier and a 58-bit accumulator. The multiplier can be dynamically bypassed, and two 58-bit inputs can feed a single-instruction multiple-data (SIMD) arithmetic unit (dual 24-bit or quad 12-bit add/subtract/accumulate), or a logic unit that can generate any one of ten different logic functions on the two operands.

New functional modes are implemented in the DSP engine, including:

  • 18 x 18 + 58 two's complement MAC with back-to-back DSP engines
  • Single-precision floating-point (binary32) accumulation
  • Three-element two's complement vector dot product with accumulate or post-add in INT8 mode

For more information about the DSP engine, see the Versal Adaptive SoC DSP Engine Architecture Manual (AM004).