I2C Controller

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The I2C controllers are multi-functional and can operate over a clock frequency range up to 400 kb/s. The controller supports multi mode for 7-bit and extended 10-bit addressing. The controllers are compatible with the Inter-integrated Circuit (IIC) specification.

In master mode, a transfer can only be initiated by software writing the address into the address register. The software is notified of any available received data by an interrupt or a transfer complete interrupt. If the hold bit is set, the I/O interface holds the clock signal (SCL) Low until after the data is transmitted to support slow software response. The controller can be programmed to use both normal addressing and extended addressing. The extended addressing is only supported in management mode.

In monitor mode, the controller is the bus manager and continues to attempt a transfer to a particular destination device until the it responds with an ACK or until the timeout occurs.

The controller supports repeated start functionality. After the start condition, the manager can generate a repeated start. This is equivalent to a normal start and is usually followed by the target I2C address.

A common feature between the two modes is the timeout interrupt flag bit. If at any point the SCL clock signal is held Low by the source or the accessed target for more than the period specified in the timeout register, the timeout interrupt bit is set. This can generate an interrupt to the software to avoid stall conditions.