Control Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2023-10-05

Revision

1.6 English

The IPI control registers are summarized in the following table. Access to the registers are controlled by the LPD_XPPU protection unit and the IPI (see Versal Adaptive SoC Register Reference (AM012)).

Table 1. IPI Control Registers
Register Name	Offset Address	Access Type	Lockable	Description
APB_ERR_CTRL	`0x0000`	RW	Yes	APB address decode SLVERR error signal enable
APB_MISC_ISR APB_MISC_IMR APB_MISC_IER APB_MISC_IDR	`0x0010 0x001C 0x0018 0x001C`	R, W1C R W W	All except ISR	Access violation and ECC error interrupt status, mask, enable and disable
LOCK	`0x0090`	RWSO	NA	Locks write access to all IPI registers except the ISR
SAFETY_CHK	`0x0030`	RW	No	Safety check registers
ERR_STATUS1_LO ERR_STATUS1_HI ERR_STATUS2	`0x0028 0x0038 0x003C`	R	NA	Address and ID of error transaction
SMID_00 SMID_01 SMID_02 SMID_03	`0x0040`+	R	NA	SMID identification for: PSM read/write PSM read-only PMC read/write PMC read-only
SMID_04 SMID_05 etc. SMID_19	`0x0050`+	RW	Yes	System management identification for software defined sources
IPI_ECC_CTRL	`0x0094`	RW	Yes	ECC control
IPI_ECC_CE_FFA IPI_ECC_CE_FFD IPI_CE_FFE	`0x0098`+	R	Yes	First failing address, data and ECC register access with correctable error
IPI_ECC_UE_FFA IPI_ECC_UE_FFD IPI_UE_FFE	`0x00A4`+	R	Yes	First failing address, data and ECC register access with un-correctable error
IPI_FI_CNTR IPI_FI_D IPI_FI_S	`0x00B0`+		Yes	Fault injection count, data, and syndrome
IPI_APER_TZ_000 IPI_APER_TZ_001 IPI_APER_TZ_002 IPI_APER_TZ_003 IPI_APER_TZ_004 IPI_APER_TZ_005 IPI_APER_TZ_006 IPI_APER_TZ_007 IPI_APER_TZ_008	`0x00BC`+	RW	Yes	Source agent message buffer TrustZone security access settings: 0: secure access required 1: non-secure
TZ_APER_INTR	`0x00DC`	RW	Yes	Interrupt register security access settings for all agents

Register Write Lock Bit

The IPI registers can only be configured by a TrustZone secure transaction. The secure transaction is routed through the LPD_XPPU protection unit to make sure the transaction host has access privileges before it is allowed to reach the IPI programming interface with its additional restrictions.

Writes to the IPI registers can be blocked by setting the LOCK [ReqWrDis] lock bit = 1. Once this bit is set, it can only be cleared by a POR.

After the lock bit is set, many of the registers can no longer be written to until a POR occurs. The lockability of the registers is shown in the Control Registers table.