The DST DMA interrupts in the DMA_DST_ISR register are summarized in the following table. The status bits show the raw (before the mask) interrupt event. Each interrupt is cleared by writing a 1 to the bit (W1C).
| Interrupt | Bit | Description |
|---|---|---|
| [DONE] | 1 | DMA is done and all data is sent; BRESP received |
| [AXI_BRESP_ERR] | 2 | DMA write generated a BRESP error on AXI |
| [TIMEOUT_STRM] | 3 | Timeout counter 2 expired; data from SRC DMA stalled |
| [TIMEOUT_MEM] | 4 | Timeout counter 1 expired; AXI interface stalled |
| [THRESH_HIT] | 5 | FIFO reached threshold limit |
| [INVALID_APB] | 6 | APB programming interface address decode error |
| [FIFO_OVERFLOW] | 7 | FIFO overflow detected |