Read interrupt status register |
ISR, 0x10
|
All |
9:0 |
Read operation |
Write back interrupt status register |
ISR, 0x10
|
All |
9:0 |
Clear bits detected as set |
Get the enabled interrupts |
IMR, 0x20
|
All |
9:0 |
Read operation |
ISR & IMR |
Check if hold bit is set (isHold) |
Control, 0x00
|
HOLD |
4 |
Read operation |
If send operation
&& (ISR & [COMP]) |
Send data (see Master Send Data). |
If receive operation
&& (ISR & [COMP]) || (ISR & [DATA). |
Perform the following
operations until receive data valid mask is set (loop-1
started). |
Read status register |
Status, 0x04
|
All |
8:0 |
Read operation |
Clear hold bit if not needed |
Control, 0x00
|
HOLD |
4 |
0 |
Receive byte |
Data, 0x0C
|
DATA |
7:0 |
Read operation |
Loop-1 Ended |
If receive byte count
is >0 and bytes still need to be received. |
Read interrupt status register |
ISR, 0x10
|
All |
9:0 |
Read operation |
Write back interrupt status register |
ISR, 0x10
|
All |
9:0 |
Clear bits detected as set |
If receive byte count > maximum transfer size
then setup transfer size |
Transfer_Size, 0x14
|
Transfer_Size |
7:0 |
Maximum transfer size |
Else program with required transfer size |
Transfer_Size, 0x14
|
Transfer_Size |
7:0 |
Required transfer size |
Enable interrupts |
IER, 0x24
|
ARB_LOST, RX_OVF, NACK, DATA, COMP |
9, 5, 2, 1 and 0 |
227h
|
Clear hold bit if all interrupts
attended |
Control, 0x00
|
HOLD |
4 |
0 |
Clear hold bit if slave ready interrupt is
triggered |
Control, 0x00
|
HOLD |
4 |
0 |
Clear hold bit if any other interrupts occurred
(event errors) |
Control, 0x00
|
HOLD |
4 |
0 |