FPD Block Resets

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

There are several reset controls resets within the APU MPCores, the PL to PS interfaces, FPD debug logic, and peripherals. Blocks can individually be reset as listed in the following table.

The reset registers for the FPD blocks are normally accessed by the PSM. Prior to asserting a reset, the PLM might put the affected logic into a quiescent state. The application software can request that one or more FPD blocks be reset using the PSM Global Registers. The PSM firmware can control interconnect traffic to halt new transactions and allow any active traffic to finish, if possible. If traffic stalls, this can be detected by the transaction timeout feature on the interconnect egress ports.

Table 1. Individual FPD Block Resets
Functional Unit Reset Name CRF Registers Notes

APU0 and APU1 cores

APU_RST RST_APU Register [APU0], [APU1]  
APU_DUAL_CSR register module      
APU GIC unit      
APU GIC x11 register modules APU_GIC_RST [APU_GIC]  
APU L2 cache APU_L2_RST [APU_L2]  
APU0 and APU1 power status  


PL to PS Interfaces


  PL_AFI_APB [Sw_Reset]  
CoreSight Debug Logic
FPD CoreSight debug logic   RST_DBG_FPD [RESET]  
FPD system watchdog timer   RST_FPD_SWDT [RESET]