The USB reference clock and core reset are controlled by the CRL register module. The base address for the CRL register module is 0xFF5E_0000.
| Register Name | Offset Address | Access Type | Description |
|---|---|---|---|
| Reference Clock | |||
|
|
RW | Reference clock control from LPD clock controller | |
| Controller Reset | |||
|
|
RW | Controller reset from LPD reset controller | |