Event Timer Functional Model

Versal Adaptive SoC Technical Reference Manual (AM011)

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Event Timer Mode

The event control timer operates by having an internal 16-bit counter clocked by the local bus clock that resets to 0 during the non-counting phase of the external pulse and increments during the counting phase of the external pulse.

The event control timer registers (e.g., TTCn_EVENT_CONTROL_TIMER_1 ( EVT_CTRL_TMR1 ) control the behavior of the internal counter.

  • [E_En] bit: when 0, immediately resets the internal counter to 0, and stops incrementing
  • [E_Lo] bit: specifies the counting phase of the external pulse
  • [E_Ov] bit: specifies how to handle an overflow at the internal counter (during the counting phase of the external pulse)
    • 0: overflow causes [E_En] to be 0 (see the [E_En] bit description)
    • 1: overflow causes the internal counter to wrap around and continues incrementing
    • When an overflow occurs, an interrupt is always generated (subject to further enabling through another register)

The event register is updated with the non-zero value of the internal counter at the end of the counting-phase of the external pulse. The event register shows the widths of the external pulse, measured in number of cycles of clock cycles. If overflow occurs, the event register is not updated and maintains the old value.