PMC DMA Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID: AM011
Release Date: 2023-10-05
Revision: 1.6 English

The following table lists the PMC DMA registers.

Table 1. PMC DMA Registers
Name	Offset	Type	Description
SRC_ADDR_L	0x000	Mixed	Source mem address (LSBs) for DMA memory → stream data transfer
SRC_SIZE	0x004	Mixed	DMA transfer payload for DMA memory → stream data transfer
SRC_STATUS	0x008	Mixed	General SRC DMA Status
SRC_CTRL1	0x00C	Mixed	General SRC DMA Control Register 1
SRC_CRC0	0x010	RW	SRC DMA Pseudo CRC Bits[31:0]
SRC_ISR	0x014	Mixed	SRC DMA Interrupt Status
SRC_IER	0x018	Mixed	SRC DMA Interrupt Enable
SRC_IDR	0x01C	Mixed	SRC DMA Interrupt Disable
SRC_IMR	0x020	Mixed	SRC DMA Interrupt Mask
SRC_CTRL2	0x024	Mixed	General SRC DMA Control Register 2
SRC_ADDR_U	0x028	Mixed	Source mem address (MSBs) for DMA memory → stream data transfer
SRC_CRC1	0x02C	RW	SRC DMA Pseudo CRC Bits[63:32]
SRC_CRC2	0x030	RW	SRC DMA Pseudo CRC Bits[95:64]
SRC_CRC3	0x034	RW	SRC DMA Pseudo CRC Bits[127:96]
DST_ADDR_L	0x800	Mixed	Destination mem address (LSBs) for DMA stream → memory data transfer
DST_SIZE	0x804	Mixed	DMA transfer payload for DMA stream → memory data transfer
DST_STATUS	0x808	Mixed	General DST DMA Status
DST_CTRL1	0x80C	RW	0x803FFA00 General DST DMA Control
DST_ISR	0x814	Mixed	DST DMA Interrupt Status Register
DST_LEN	0x818	Mixed	DST DMA Interrupt Enable
DST_IDR	0x81C	Mixed	DST DMA Interrupt Disable
DST_IMR	0x820	Mixed	DST DMA Interrupt Mask
DST_CTRL2	0x824	Mixed	General DST DMA Control Register 2
DST_ADDR_U	0x828	Mixed	Destination mem address (MSBs) for DMA stream → memory data transfer
SRC_QoS	0x830	Mixed	SRC channel QOS configuration
DST_QoS	0x834	Mixed	DST channel QOS configuration
PMCDMA_SSS_CFG	0xFF4	RW	Configuration register output for the SS interface
SAFETY_CHK	0xFF8	RW	Safety check register