The PSM local registers are only accessible to the PSM firmware. These registers help to control and status the following.
- APU and RPU processor power controls
- Cache and embedded memory power controls
- Isolation controls
- Power states
PSM Local Register Set
The PS power island control and status registers are listed in the following table.
Register Name | Offset Address | Access Type | Description |
---|---|---|---|
|
RW |
APU cores power control and status | |
|
RW |
RPU power control and status | |
|
RW |
L2 cache power control/status and chip enables | |
|
RW |
OCM power control/status and chip enables | |
|
RW |
RPU power control/status and chip enables | |
|
RW |
GEM power control/status and chip enables | |
0x00F0
|
RW | Isolations: LPD-FPD and LPD-XRAM | |
0x0100
|
RW | Power status of LPD blocks | |
|
R, W1C |
APB address decode error interrupt | |
0x0418
|
R | APU wake for status on APU cores and L2 cache |