The I/O buffer pin banks are listed in the following table.
| Bank Name | Pin Count | Buffer Type | Description |
|---|---|---|---|
| PMC DIO Bank | 17 | Digital | Dedicated I/O with POR_B, REF_CLK, JTAG, I3C, and boot mode. |
| PMC DIO_A Bank | 4 | Analog | PMC system monitor. |
| UFS | 4 | GTs | Unified flash storage clock and data transceivers in PMC |
|
PMC MIO Bank 0 |
52 | Digital |
Multiplexed I/O for boot devices and peripherals in the PMC and LPD IOPs. See Multiplexed I/O Signal Pins. |
| LPD MIO Bank | 26 | Digital | |
| PL X5IO | 54 per bank | XP IOB | The X5IO banks are normally used by the DDRMC5e, but are available for use by the PL except for the X5IO banks located in the corners of the die. |
| PL PSIO | Varies | Digital | Multiple banks of LVCMOS PSIO buffers connect PL to device pins. |
| GTYPM | Varies | Transceiver | GTs for PS High-speed Connectivity units. |