TX Descriptor Entry Words

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The following table includes details of the transmit buffer descriptor list.

Table 1. GEM TX Descriptor, Words 0 and 1
Bit Function
Word 0
31:0 Byte address of buffer.
Word 1
31 Used: must be zero for the controller to read data to the transmit buffer. After it is successfully transmitted, the controller sets this bit to one for the first buffer of a frame. Software must clear this bit before the buffer can be used again.
30 Wrap: marks last descriptor in the transmit buffer descriptor list. This can be set for any buffer within the frame.
29 Retry limit exceeded, transmit error detected.
28 Always set to 0.
27 Transmit frame corruption due to AXI error: set if an error occurs midway while reading through the transmit frame from the AXI, including RESP errors, and buffers exhausted mid-frame. If the buffers run out during transmission of a frame, then transmission stops, the FCS is incorrect, and tx_er is asserted.
26 Late collision, transmit error detected. Late collisions force this status bit to be set in gigabit mode.
25:24 Reserved.
23 For extended buffer descriptor mode. This bit indicates a timestamp is captured in the buffer descriptor. Otherwise the bit is reserved.

Transmit IP/TCP/UDP checksum generation offload errors:

000b: No error.

001b: Packet is identified as VLAN type, but header is not fully complete, or has an error in it.

010b: Packet is identified as SNAP type, but header is not fully complete, or has an error in it.

011b: Packet is not of IP type, or IP packet was invalidly short, or IP is not of type IPv4/IPv6.

100b: The packet is not identified as VLAN, SNAP, or IP.

101b: Non-supported packet fragmentation occurred. For IPv4 packets, IP checksum is generated and inserted.

110b: Packet type detected is not TCP or UDP. TCP/UDP checksum is therefore not generated. For IPv4 packets, the IP checksum is generated and inserted.

111b: A premature end of packet is detected and the TCP/UDP checksum cannot be generated.

19:17 Reserved.

No CRC to be appended by the MAC. When set this bit implies that the data in the buffers already contains a valid CRC and no CRC or padding is appended to the current frame by the MAC.

This control bit must be set for the first buffer in a frame and is ignored for the subsequent buffers of a frame. This bit must be clear when using the transmit IP/TCP/UDP checksum generation offload, otherwise checksum generation and substitution does not occur.

15 Last buffer, this bit (when set) indicates that the last buffer in the current frame is reached.
14 Reserved.
13:0 Length of buffer.
Table 2. GEM TX Descriptor Word Summary
64-bit Addressing for AXI DMA Interface 32-bit Addressing for External FIFO Interface Field Description
Word 0 Word 0 31:0 Byte address of buffer
Word 1 Word 1 31:0 Miscellaneous fields
Word 2 - 31:0 Upper 32-bit address of the data buffer
Word 3 Word 2 31:0 Not used
Word 4 Word 3


Timestamp seconds [1:0]
Timestamp, nanoseconds

Word 5 -


Timestamp seconds [5:2]