I/O Interface Control Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The I/O interface controls are located in the SD_eMMC and PMC_IOP_SLCR register modules. The majority of these registers are for configuring the SDx_CLK output to the flash memory device.

Note: The system reference clocks that drive the DIV_CLK and DLL modules are listed in the table in the System-Related Registers section.

SD_eMMC Register Module

The following I/O interface control registers are included in the SD_EMMC register module.

Note: These registers are defined with 16-bit data widths. However, all registers are accessed as 32-bit read/write transfers with addresses aligned on a 32-bit boundary.
Table 1. SD_eMMC I/O Interface Control Registers in the SD_eMMC Register Module
Register Name Width Offset Address Access Type Description
SD_CLK Control and Status
CLK_CTRL 16 0x02C Mixed Clock frequency control and state
Read Preset Values







Read the preset values for SD_CLK frequency, clock generator, and driver strength select value.

PMC_IOP_SLCR Register Module

The I/O clocks are sourced from either the DIV_CLK or DLL clock modules.

SD_eMMC are further configured by several registers in the PMC_IOP_SLCR register set. All registers listed in the following table are defined as 32 bits.

Table 2. SD_eMMC I/O Interface Control Registers in the PMC IOP SLCR Register Module
Register Name Access Type Description
SD_eMMC Controller 0 SD_eMMC Controller 1
Clock and Control
SD0_Clk_Ctrl SD1_Clk_Ctrl RW SD feedback clock routing
SD0_Ctrl SD1_Ctrl RW Controller mode: SD or eMMC







RW Configuration registers


















Initialization for SD:
Init preset
Default speed
High speed

Miscellaneous Registers
SD0_DLL_Ctrl SD1_DLL_Ctrl Mixed SD DLL status
SD0_Rx_Tuning_Sel SD1_Rx_Tuning_Sel R DLL RX clocking


SD1_DLL_DivMap RW DLL divider mapping
SD0_CD_Ctrl SD1_CD_Ctrl RW SD card detect







RW Maximum current: 1.8, 3.0, and 3.3V