Arm DAP Registers - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The Versal adaptive SoCs provide Arm DAP registers listed in the following table.

Table 1. Arm DAP Registers
Register Name Register Length Description
BYPASS 1-bit Bypasses the Arm DAP
IDCODE 32-bit Captures the Arm DAP IDCODE (6BA00477h)
INSTRUCTION 4-bit Holds the current instruction opcode. The total Versal adaptive SoC instruction register length is the DAP (4-bit instruction register length) + TAP (6-bit instruction register length).