JTAG Register Reference

Versal Adaptive SoC Technical Reference Manual (AM011)

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The Versal adaptive SoCs provide JTAG registers that can be accessed through the JTAG interface for boundary-scan operations and debug. Several of the JTAG registers provide valuable status indicators for the device start-up and boot. The JTAG TAP registers in the Versal adaptive SoC are listed in the following table

Table 1. JTAG Registers
Register Name Register Length Description
BOUNDARY Varies per device Controls and observes input, output, and output enable
BYPASS 1-bit Bypasses the device
ERROR_STATUS 160-bit Captures the error management status for the PMC
EXTENDED_IDCODE 32-bit Captures the device extended IDCODE
  • Holds the current instruction opcode and captures internal device status
  • Total Versal adaptive SoC instruction register length is DAP (4-bit instruction register length) + TAP (6-bit instruction register length)
  • Connects the JTAG pins to the SBI when using the JTAG TAP instructions JCONFIG and JRDBK
  • These JTAG TAP instructions write or read a programmable device image into the Versal adaptive SoC
  • The JTAG_CONFIG data register does not support pausing during data shifting via temporary transitions to the JTAG TAP DR-PAUSE state. If data shifting must be paused, then pause by stopping the TCK clock while keeping the JTAG TAP in the DR-SHIFT state.
DNA 128-bit Captures the device DNA value
SECURE_DEBUG 32-bit Shifts in the authenticated data packet to authenticate in secure mode
JTAG_STATUS 36-bit Captures the platform management controller overall status
SYSTEM_RESET 1-bit Issues a Versal adaptive SoC PMC_SRST
USER_DEFINED (USER1, USER2, USER3, USER4) Design specific Design-specific register
USERCODE 32-bit Captures the user-designated value
  1. The SSI technology devices JTAG TAP register length varies by device and controller state. See SSI Multiple Super Logic Regions.