Each MIO pin buffer has several register controls:
- Internal pull-up and pull-down
- Schmitt trigger input enable
- Output enable
- Output drive strength
The characteristics are individually controlled.
-
PMC_IOP_SLCR
register module for the PMC MIO pins, PMC MIO bank 0 and 1
- PMC MIO pins 0 to 25, PMC MIO bank 0
- PMC MIO pins 26 to 51, PMC MIO bank 1
-
LPD_IOP_SLCR
register module for the LPD MIO pins
- LPD MIO pins 0 to 25, LPD MIO bank 2
The control registers are listed in these sections: