The following tables list the system errors routed to the PMC system error accumulator module (EAM).
| Error Name | PMC_ERR1_STATUS (PMC_GLOBAL) Register bit | JTAG Error Bit | Description |
|---|---|---|---|
| reserved | PMC_ERR1_STATUS[0] | 63 | reserved |
| BootROM NCR | PMC_ERR1_STATUS[1] | 62 | BootROM non-correctable error; set during boot |
| PLM CR | PMC_ERR1_STATUS[2] | 61 | PLM boot correctable error; set during boot. See PMC_GLOBAL.PLM_FW_ERR register. |
| PLM NCR | PMC_ERR1_STATUS[3] | 60 | PLM boot non-correctable error; set during boot. See PMC_GLOBAL.PLM_FW_ERR register. |
| GSW CR | PMC_ERR1_STATUS[4] | 59 | General software correctable error; set by any processor after boot |
| GSW NCR | PMC_ERR1_STATUS[5] | 58 | General software non-correctable error; set by any processor after boot |
| CFU | PMC_ERR1_STATUS[6] | 57 | CFU error |
| CFRAME | PMC_ERR1_STATUS[7] | 56 | CFRAME error |
| PSM CR | PMC_ERR1_STATUS[8] | 55 | PSM correctable error |
| PSM NCR | PMC_ERR1_STATUS[9] | 54 | PSM non-correctable error |
| DDRMC MB CR | PMC_ERR1_STATUS[10] | 53 | DDRMC MicroBlazeâ„¢ correctable ECC |
| DDRMC MB NCR | PMC_ERR1_STATUS[11] | 52 | DDRMC MicroBlaze non-correctable ECC |
| NOC CR | PMC_ERR1_STATUS[12] | 51 | NoC correctable error |
| NOC NCR | PMC_ERR1_STATUS[13] | 50 | NoC non-correctable error |
| NOC user | PMC_ERR1_STATUS[14] | 49 | NoC user error |
| MMCM lock | PMC_ERR1_STATUS[15] | 48 | MMCM lock error |
| AI Engine CR | PMC_ERR1_STATUS[16] | 47 | AI Engine correctable error |
| AI Engine NCR | PMC_ERR1_STATUS[17] | 46 | AI Engine non-correctable error |
| DDRMC MC ECC CR | PMC_ERR1_STATUS[18] | 45 | DDRMC memory correctable ECC |
| DDRMC MC ECC NCR | PMC_ERR1_STATUS[19] | 44 | DDRMC memory non-correctable ECC |
| GT CR | PMC_ERR1_STATUS[20] | 43 | GT correctable error |
| GT NCR | PMC_ERR1_STATUS[21] | 42 | GT non-correctable error |
| SYSMON CR | PMC_ERR1_STATUS[22] | 41 | System monitor correctable error |
| SYSMON NCR | PMC_ERR1_STATUS[23] | 40 | System monitor non-correctable error |
| User PL0 | PMC_ERR1_STATUS[24] | 39 | User-defined PL error |
| User PL1 | PMC_ERR1_STATUS[25] | 38 | User-defined PL error |
| User PL2 | PMC_ERR1_STATUS[26] | 37 | User-defined PL error |
| User PL3 | PMC_ERR1_STATUS[27] | 36 | User-defined PL error |
| NPI module | PMC_ERR1_STATUS[28] | 35 | NPI Module reported error |
|
SSIT Error 3 |
PMC_ERR1_STATUS[29] |
34 |
Stacked silicon integrated technology with super logic regions (SLR) errors |
| Error Name | PMC_ERR2_STATUS (PMC_GLOBAL) Register bit | JTAG Error Bit | Description |
|---|---|---|---|
| PMC APB | PMC_ERR2_STATUS[0] | 31 |
General purpose PMC error, can be triggered by any of the following peripherals: * PMC Global Registers * PMC Clock & Reset (CRP) * PMC IOU Secure SLCR * PMC IOU SLCR * BBRAM Controller * PMC Analog Control Registers * RTC Control Registers |
| PMC BootROM | PMC_ERR2_STATUS[1] | 30 | BootROM validation error |
| RCU hardware | PMC_ERR2_STATUS[2] | 29 | RCU hardware error |
| PPU hardware | PMC_ERR2_STATUS[3] | 28 | PPU hardware error |
| PMC parity | PMC_ERR2_STATUS[4] | 27 | PMC main and IOP interconnect parity errors |
| PMC CR | PMC_ERR2_STATUS[5] | 26 |
RCU and PPU correctable RAM errors: |
| PMC NCR | PMC_ERR2_STATUS[6] | 25 | RCU and PPU non-correctable RAM error |
| PMC SYSMON voltage |
PMC_ERR2_STATUS[7] |
24 |
Remote system monitor (SYSMON) voltage alarms: |
| reserved |
PMC_ERR2_STATUS[12] |
19 |
reserved |
| PMC SYSMON temperature |
PMC_ERR2_STATUS[15] |
16 |
Remote system monitor (SYSMON) temperature alarms: |
| CFI NCR | PMC_ERR2_STATUS[17] | 14 |
CFI non-correctable error |
| SEU CRC | PMC_ERR2_STATUS[18] | 13 | CFRAME SEU CRC error |
| SEU ECC | PMC_ERR2_STATUS[19] | 12 | CFRAME SEU ECC error |
| reserved | PMC_ERR2_STATUS[20] | 11 | reserved, returns 0 |
| reserved | PMC_ERR2_STATUS[21] | 10 | reserved, returns 1 |
| RTC alarm | PMC_ERR2_STATUS[22] | 9 | RTC alarm error |
| NPLL | PMC_ERR2_STATUS[23] | 8 | PMC NPLL lock error; asserted while locking or when lock is lost |
| PPLL | PMC_ERR2_STATUS[24] | 7 | PMC PPLL lock error; asserted while locking or when lock is lost |
| Clock monitor | PMC_ERR2_STATUS[25] | 6 | PMC clock monitor (ClkMon) error signal driven by CRP.CLKMON_ISR.status register |
| PMC timeout | PMC_ERR2_STATUS[26] | 5 | PMC interconnect switch timeout errors; from mission and timeout interrupt status registers in ePorts |
| PMC XMPU | PMC_ERR2_STATUS[27] | 4 | PMC_XMPU error detection signal; includes read permission, write permission, and security access violations |
| PMC XPPU | PMC_ERR2_STATUS[28] | 3 | PMC XPPU error detection; includes SMID not found, SMID parity error, read permission, SMID access, and TrustZone access violations |
|
SSIT error 0 |
PMC_ERR2_STATUS[29] |
2 |
Stacked silicon interconnect technology SLR errors; from SSI technology super logic regions 0 to 2 |