CoreSight Architecture

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
Release Date
1.6 English

The CoreSightâ„¢ debug (DBG) functionality has several entry points.

  • DAP controller on the JTAG chain
  • DPC switch
  • PMC main switch

The width of the CoreSight output trace data bus can be 1, 2, 4, 8, or 16 bits wide. Higher bandwidth output can be obtained using the data packet controller (DPC) high-speed debug port (HSDP).