TPIU I/O Signals - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2025-07-28
Revision
1.8 English

The PS trace output data from the TPIU has routing options that are selected using the EXTCTL_Out_Port register:

  • PMC MIO multiplexer (two options), clocked by TPIU with double data rate (DDR)
  • EMIO to the PL, clocked by PL with single data rate (SDR)
  • Trace TPIU bridge to DPC, clocked by TPIU with SDR

The signals for TPIU are listed in the following table. The data width should be programmed to be 1, 2, 4, 8, 16, or 32 bits.

Table 1. TPIU Trace I/O Signals
MIO EMIO
Signal Name I/O MIO-at-a-Glance Pins Signal Name I/O
TRACE_CLK O CLK PLPS_TRACE_CLK I
TRACE_CTRL O CTL PSPL_TRACE_CTL O
TRACE_DATA[0] O D0 PSPL_TRACE_DATA [31:0] O
TRACE_DATA[1] O D1
TRACE_DATA[2:3] O D2,3
TRACE_DATA[4:7] O D4-7
TRACE_DATA[8:15] O D8-15