The following table lists the characteristics of the supervised and autonomous boot interfaces.
The pins used for each MIO boot interface are shown as shaded cells in the tables in the MIO-at-a-Glance Tables section.
The interfaces are described in detail in various other sections of the TRM.
| Boot Interface | Mode [3:0] Pins | Secure Boot Capable | Data Bus Width | Description |
|---|---|---|---|---|
| Interfaces controlled by external devices (supervised) | ||||
| JTAG |
0000
|
No | 1-bit | Dedicated JTAG interface, see JTAG Boot Mode. |
| SelectMAP |
1010
|
Yes | 8-bit, 16-bit, 32-bit | SelectMAP parallel bus interface, see SelectMAP Boot Mode. |
| Interfaces controlled by on-chip controllers (autonomous) | ||||
| OSPI |
1000
|
Yes | 8-bit | OSPI interface supports single and dual-stacked flash devices, see OSPI Flash Boot Mode. |
| QSPI24 |
0001
|
Yes | 1-bit, 2-bit, 4-bit (single or dual-stacked) 8-bit (dual-parallel) |
QSPI interface supports the 24-bit (3-byte) flash addresses 1 , see QSPI Flash Boot Mode. |
| QSPI32 |
0010
|
Yes | 1-bit, 2-bit, 4-bit (single or dual-stacked) 8-bit (dual-parallel) |
QSPI interface supports the 32-bit (4-byte) flash addresses. 32-bit flash addressing is required to address flash devices that are greater than 128 Mb. 1 |
| eMMC1 v4.51 |
0110
|
Yes | 1-bit, 4-bit, 8-bit | eMMC interface supports eMMC 4.51 at 1.8V, see eMMC v4.51 Boot Mode. |
| SD0 v3.0 |
0011
|
Yes | 4-bit | SD interface supports SD 3.0 with a required SD 3.0 compliant external level shifter, see SD Flash Boot Mode. |
| SD1 v2.0 |
0101
|
Yes | 4-bit | SD interface supports SD 2.0, see SD Flash Boot Mode. |
| SD1 v3.0 |
1110
|
Yes | 4-bit |
SD interface supports SD 3.0 with a required SD 3.0 compliant external level shifter, see SD Flash Boot Mode. |
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