Control and Status

Control and Status - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2023-10-05

Revision

1.6 English

The GEM control registers are summarized in the following table.

Table 1. GEM Control and Status Registers
Register Name	Access Type	Description
Controller and MAC Configuration
Network_Control Network_Config Network_Status	RW RW R	Network control for RX and TX MACs Network configuration for MACs Network status for PHY management MDIO, priority flow control, LPI, and AXI
Pause_Time	R	Received pause quantum register
Tx_Pause_Quantum	RW	Transmit pause quantum register
PHY Management
PHY_Manage	RW	PHY maintenance
DMA and Buffer Descriptor Control
DMA_Config Tx_Status Tx_Q_Ptr Tx_Q1_Ptr Rx_Status Rx_Q_Ptr Rx_Q1_Ptr DMA_Addr_Mask	RW WTC RW RW WTC RW R RW	DMA configuration TX path status TX buffer data start address TX buffer descriptor list address RX path status RX buffer data start address RX buffer descriptor list address RX DMA data buffer address mask
Interrupts
APB_Misc_ISR APB_Misc_IER APB_Misc_IDR , APB_Misc_IMR	WTC W R	Interrupt status, enable/disable, and mask
Miscellaneous
PBuf_Tx_CutThru , PBuf_Rx_CutThru	RW	Partial store and forward is only applicable when using the DMA configured in the SRAM-based packet buffer mode. It is not available when using multi-buffer frames. RX partial store and forward.
Jumbo_Max_Length	RW	Maximum jumbo frame size
Ext_FIFO_Interface	RW	Enable external FIFO interface
AXI_Pipeline	RW	AXI maximum pipeline
RSC_Control	RW	Used to enable receive side coalescing on queues 1-15
Intr_Moderation Sys_WakeTime Fatal_Intr_Select	RW	TX and RX moderation control Pause transmission after wake Fatal, non-fatal interrupt select
Lockup_Config Lockup_Config3 RxMAC_Lockup_Time	RW	Lock-up detection and recovery configuration DMA TX lock-up enable control Receive MAC lock-up detection time
Rx_Watermark	RW	RXFIFO watermark levels for pause frames
Hash_L , Hash_U	RW	Hash register lower 31:0 Hash register upper 63:32
Address Filtering and ID Match
Spec_Addr1_L {1:4} Spec_Addr1_U {1:4} Mask_Addr1_L Mask_Addr1_U Spec_ID1_Match {1:4}	RW	Specific address lower 31:0 Specific address upper 47:32 Specific address mask bottom 31:0 Specific address mask top 47:32 Specific type ID match
Wake_On_Lan	RW	Wake on LAN
Stretch_Ratio	RW	Inter-packet gap stretch
Stacked_VLAN	RW	User defined VLAN, stacked
Tx_PFC_Pause	RW	Transmit PFC pause
Rx_PTP_Unicast Tx_PTP_Unicast TSU_Compare_nS TSU_Compare_Sec_L TSU_Compare_Sec_U	RW	Timestamp control
TSU_PTP_Tx_Sec_U TSU_PTP_Rx_Sec_U TSU_Peer_Tx_Sec_U TSU_Peer_Rx_Sec_U	R	Timestamp status
Timestamp Unit, Precision Time Protocol
TSU_Timer_NSec TSU_Adjust TSU_Increment	RW	IEEE Std 1588: second, nanosecond counter and adjustment, increment
TSU_Timer_SubnSec_L tsu_timer_msb_sec TSU_Timer_Sec TSU_Strobe_Sec_U TSU_Strobe_Sec_L TSU_Strobe_nSec ¹	RW RW R R R	Timestamp timer control and strobe value
TSU_PTP_Tx_Sec TSU_PTP_Tx_nSec TSU_PTP_Rx_Sec TSU_PTP_Rx_nSec TSU_Peer_Tx_Sec TSU_Peer_Tx_nSec GEM.TSU_Peer_Rx_Sec TSU_Peer_Rx_nSec	R	IEEE Std 1588: TX and RX normal/peer second, nanosecond counter
Low-Power Idle Control
RxLPI_Count RxLPI_AccTime , TxLPI_Count TxLPI_AccTime	R R R R	Transaction count and time
Design Configuration
IP_Config1	R	Design configuration registers 1 to 12
Miscellaneous
CBS_Control CBS_IdleQueue_A CBS_IdleQueue_B	RW	Credit-based shaping control
TxBuffer_Addr_U , RxBuffer_Addr_U	RW	Descriptor queue base address
Tx_BD_Control Rx_BD_Control	RW	Timestamp insertion mode
ScreenType1_reg0 , ScreenType1_reg1 ScreenType1_reg2 , ScreenType1_reg3 , ScreenType2_reg0 , ScreenType2_reg1 , ScreenType2_reg2 , ScreenType2_reg3	RW	Screen 1 and 2 control
Tx_Sched_Ctrl BW_Rate_Limit TxQueue_SegAlloc	RW	TX queue scheduling mode, bandwidth weighing, and space allocation
Queue_ISR , Queue_IER , Queue_IDR , Queue_IMR	WTC W R	Queue 1 status and interrupt enable, disable, mask
ScreenType2_Enet_reg0 , ScreenType2_Enet_reg1 , ScreenType2_Enet_reg2 , ScreenType2_Enet_reg3	RW RW	Screen type 2 Ethernet type compare registers
ScreenComp0_wd0 , ScreenComp0_wd1 ScreenComp1_wd0 , ScreenComp1_wd1 ScreenComp2_wd0 , ScreenComp2_wd1 ScreenComp3_wd0 , ScreenComp3_wd1	RW	Four screen type 2 compare functions (words 0 and 1)
EnST_StartTime_Q0 , EnST_StartTime_Q1 , EnST_OnTime_Q0 , EnST_OnTime_Q1 , EnST_OffTime_Q0 , EnST_OffTime_Q1 , EnST_Control	RW	Queue start, open, and close times, and enable, disable
Extended Stream Identification Functions
FRER_Timeout , FRER_RedTag FRER_Control_1A , FRER_Control_1B , FRER_Stats_1A , FRER_Stats_1B Etc., for control/status 1 to 16	RW	Timeout, control, and statistics
RxQueue0_Flush , RxQueue1_Flush	RW	Queue flush
ScreenType2_RateLimit_reg0 ScreenType2_RateLimit_reg1	RW	Maximum rate limit for screen 2
The timer sync strobe registers are loaded with the value of the timer when the input signal emio_enet{0:3}_tsu_inc_ctrl[1:0] = `00b`. However, the timer sync strobe registers are updated only when emio_enet{0:3}_tsu_inc_ctrl signal toggles between `11b` and `00b`.