4 GB Processor System Address Map

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The processor system address map includes 2 GBs for DDR memory and 2 GBs for register modules, local memories, and miscellaneous access ports for the PMC and PS subsystems. The address space also includes interfaces directly from the PS to the programmable logic (PL). In some devices, the address space defines a cache coherent PCIe® module (CPM) between the PS and a PCIe-based subsystem.

Table 1. 4 GB Processor System Address Map
Destination Description Type Address Range Size (KB) Firewall
Start End
DDRMC0_region0_mem DRAM Memory Controller 0, Region 0 (lower 2 GB) mem Std 0x0000_0000 0x7FFF_FFFF 2 GB DDRMC0_XMPU
LPD_AXI_PL_mmap PS-to-PL AXI Interface from LPD mmap Std 0x8000_0000 0x9FFF_FFFF 512 MB -
FPD_AXI_PL_mmap PS-to-PL AXI Interface from FPD, lower mmap Std 0xA400_0000 0xAFFF_FFFF 192 MB -
FPD_AXI_PL_mmap PS-to-PL AXI Interface from FPD, upper mmap Std 0xB000_0000 0xBFFF_FFFF 256 MB -
OSPI_mem Octal-SPI Linear Mode memory space mem Std 0xC000_0000 0xDFFF_FFFF 512 MB LPD_XPPU (512 MB)
CPM4_XDMA_CSR CPM4 DMA control registers (XDMA) reg CPM4 0xE100_0000 0xE100_FFFF 64 KB  
PMC_LOCAL PMC Local registers reg Std 0xF004_0000 0xF004_FFFF 64 KB  
PMC_PUF PUF control registers reg Std 0xF005_0000 0xF005_FFFF 64 KB  
PPU_RAM_INSTR_mem PPU I-cache Addressable mem Std 0xF020_0000 0xF023_FFFF 256 KB  
PPU_RAM_DATA_mem PPU D-cache Addressable mem Std 0xF024_0000 0xF025_FFFF 128 KB  
PPU_IOMODULE PPU I/O Module registers reg Std 0xF028_0000 0xF028_0FFF 4 KB  
PPU_ICACHE_CTRL PPU Instruction Cache ECC control reg Std 0xF028_1000 0xF028_1FFF 4 KB  
PPU_DCACHE_CTRL PPU Data Cache ECC control reg Std 0xF028_2000 0xF028_2FFF 4 KB  
PPU_TMR_MANAGER PPU Triple Redundancy Manager reg Std 0xF028_3000 0xF028_3FFF 4 KB  
PPU_TMR_INJECT PPU Triple Redundancy Error Injection reg Std 0xF028_4000 0xF028_4FFF 4 KB  
PPU_TMR_TRACE PPU Trace reg Std 0xF030_0000 0xF030_0FFF 4 KB  
PPU_MDM PPU Debug Module control reg Std 0xF031_0000 0xF031_7FFF 32 KB  
DBG_PMC_ROM CoreSight PMC ROM reg Std 0xF080_0000 0xF080_FFFF 64 KB  
DBG_PMC_GPR CoreSight PMC GPR 1P reg Std 0xF081_0000 0xF081_FFFF 64 KB  
DBG_PMC_CTI CoreSight PMC Map Trigger and Channel interfaces reg Std 0xF08D_0000 0xF08D_FFFF 64 KB  
DBG_LPD_ROM CoreSight LPD ROM reg Std 0xF090_0000 0xF090_FFFF 64 KB  
DBG_LPD_GPR CoreSight LPD GPR 3P reg Std 0xF091_0000 0xF091_FFFF 64 KB  
DBG_LPD_FUN CoreSight LPD Merge Five Trace Streams to ATB reg Std 0xF092_0000 0xF092_FFFF 64 KB  
DBG_TSG_RW CoreSight Master Time Stamp with Read/Write reg Std 0xF099_0000 0xF099_FFFF 64 KB  
DBG_LPD_CTI CoreSight LPD Map Trigger and Channel interfaces reg Std 0xF09D_0000 0xF09D_FFFF 64 KB  
DBG_RPU0_DBG CoreSight RPU0 Built-in Debug Logic reg Std 0xF0A0_0000 0xF0A0_FFFF 64 KB  
DBG_RPU0_CTI CoreSight RPU0 Map Trigger and Channel interfaces reg Std 0xF0A1_0000 0xF0A1_FFFF 64 KB  
DBG_RPU0_ETM CoreSight RPU 0 Generate Trace reg Std 0xF0A3_0000 0xF0A3_FFFF 64 KB  
DBG_RPU1_DBG CoreSight RPU1 Built-in Debug Logic reg Std 0xF0A4_0000 0xF0A4_FFFF 64 KB  
DBG_RPU1_CTI CoreSight RPU1 Map Trigger and Channel interfaces reg Std 0xF0A5_0000 0xF0A5_FFFF 64 KB  
DBG_RPU1_ETM CoreSight RPU1 Generate Trace reg Std 0xF0A7_0000 0xF0A7_FFFF 64 KB  
DBG_FPD_ROM CoreSight FPD ROM reg Std 0xF0B0_0000 0xF0B0_FFFF 64 KB  
DBG_FPD_GPR CoreSight FPD GPR 2P reg Std 0xF0B1_0000 0xF0B1_FFFF 64 KB  
DBG_FPD_FUN CoreSight LPD Merge Six Trace Streams to ATB reg Std 0xF0B2_0000 0xF0B2_FFFF 64 KB  
DBG_FPD_ETF CoreSight FPD Embedded 32K Trace FIFO reg Std 0xF0B3_0000 0xF0B3_FFFF 64 KB  
DBG_FPD_REPL CoreSight Replicates ATB Data Stream reg Std 0xF0B4_0000 0xF0B4_FFFF 64 KB  
DBG_FPD_ETR CoreSight FPD Enable Local Trace Buffer reg Std 0xF0B5_0000 0xF0B5_FFFF 64 KB  
DBG_TPIU CoreSight Test port interface unit reg Std 0xF0B6_0000 0xF0B6_FFFF 64 KB  
DBG_STM CoreSight System Trace Module reg Std 0xF0B7_0000 0xF0B7_FFFF 64 KB  
DBG_FPD_CTI1B CoreSight FPD 1B Map Trigger and Channel interfaces reg Std 0xF0BB_0000 0xF0BB_FFFF 64 KB  
DBG_FPD_CTI1C CoreSight FPD 1C Map Trigger and Channel interfaces reg Std 0xF0BC_0000 0xF0BC_FFFF 64 KB  
DBG_FPD_CTI1D CoreSight FPD 1D Map Trigger and Channel interfaces reg Std 0xF0BD_0000 0xF0BD_FFFF 64 KB  
DBG_APU_FUN CoreSight APU Merge Two Trace Streams to ATB reg Std 0xF0C2_0000 0xF0C2_FFFF 64 KB  
DBG_APU_ETF CoreSight APU Embedded 4K Trace FIFO reg Std 0xF0C3_0000 0xF0C3_FFFF 64 KB  
DBG_APU_ELA CoreSight APU Embedded 128 Logic Analyzer reg Std 0xF0C6_0000 0xF0C6_FFFF 64 KB  
DBG_APU_CTI CoreSight APU MPCore Map Trigger and Channel reg Std 0xF0CA_0000 0xF0CA_FFFF 64 KB  
DBG_APU0_DBG CoreSight APU0 Built-in Debug Logic reg Std 0xF0D0_0000 0xF0D0_FFFF 64 KB  
DBG_APU0_CTI CoreSight APU0 Map Trigger and Channel interfaces reg Std 0xF0D1_0000 0xF0D1_FFFF 64 KB  
DBG_APU0_PMU CoreSight APU0 Processor Performance Profile reg Std 0xF0D2_0000 0xF0D2_FFFF 64 KB  
DBG_APU0_ETM CoreSight APU0 Generate Trace reg Std 0xF0D3_0000 0xF0D3_FFFF 64 KB  
DBG_APU1_DBG CoreSight APU1 Built-in Debug Logic reg Std 0xF0D4_0000 0xF0D4_FFFF 64 KB  
DBG_APU1_CTI CoreSight APU1 Map Trigger and Channel interfaces reg Std 0xF0D5_0000 0xF0D5_FFFF 64 KB  
DBG_APU1_PMU CoreSight APU1 Processor Performance Profile reg Std 0xF0D6_0000 0xF0D6_FFFF 64 KB  
DBG_APU1_ETM CoreSight APU1 Generate Trace reg Std 0xF0D7_0000 0xF0D7_FFFF 64 KB  
DBG_CPM_ROM CoreSight CPM ROM reg Std 0xF0F0_0000 0xF0F0_FFFF 64 KB  
DBG_CPM_FUN CoreSight CPM Merge Two Trace Streams to ATB reg Std 0xF0F2_0000 0xF0F2_FFFF 64 KB  
DBG_CPM_ELA2A CoreSight CPM 2A Embedded 256 Logic Analyzer reg Std 0xF0F4_0000 0xF0F4_FFFF 64 KB  
DBG_CPM_ELA2B CoreSight CPM 2B Embedded 256 Logic Analyzer reg Std 0xF0F5_0000 0xF0F5_FFFF 64 KB  
DBG_CPM_ELA2C CoreSight CPM 2C Embedded 256 Logic Analyzer reg Std 0xF0F6_0000 0xF0F6_FFFF 64 KB  
DBG_CPM_ELA2D CoreSight CPM 2D Embedded 256 Logic Analyzer reg Std 0xF0F7_0000 0xF0F7_FFFF 64 KB  
DBG_CPM_CTI2A CoreSight CPM 2A Map Trigger and Channel interfaces reg Std 0xF0FA_0000 0xF0FA_FFFF 64 KB  
DBG_CPM_CTI2D CoreSight CPM 2D Map Trigger and Channel interfaces reg Std 0xF0FD_0000 0xF0FD_FFFF 64 KB  
PMC_I2C PMC I2C controller reg Std 0xF100_0000 0xF100_FFFF 64 KB  
OSPI Octal-SPI control reg Std 0xF101_0000 0xF101_FFFF 64 KB  
PMC_GPIO General Purpose I/O in PMC reg Std 0xF102_0000 0xF102_FFFF 64 KB  
QSPI Quad-SPI control reg Std 0xF103_0000 0xF103_FFFF 64 KB  
SD_eMMC0 SD/eMMC controller 0 reg Std 0xF104_0000 0xF104_FFFF 64 KB  
SD_eMMC1 SD/eMMC controller 1 reg Std 0xF105_0000 0xF105_FFFF 64 KB  
PMC_IOP_SLCR PMC IOP SLCR registers, non-secure reg Std 0xF106_0000 0xF106_FFFF 64 KB  
PMC_IOP_SLCR_SECURE PMC IOP SLCR registers, secure reg Std 0xF107_0000 0xF107_FFFF 64 KB  
PMC_IOP_INT_GPV PMC IOP Interconnect Global Programmers View (GPV) reg Std 0xF108_0000 0xF108_FFFF 64 KB  
PMC_RAM_CSR PMC On-chip Memory configuration reg Std 0xF110_0000 0xF110_FFFF 64 KB  
PMC_GLOBAL PMC Global registers reg Std 0xF111_0000 0xF115_FFFF 320 KB  
PMC_ANLG PMC analog voltage monitoring control reg Std 0xF116_0000 0xF119_FFFF 256 KB  
PMC_JTAG_CSR PMC JTAG TAP control reg Std 0xF11A_0000 0xF11B_FFFF 128 KB  
PMC_DMA0_CSR PMC DMA 0 Control reg Std 0xF11C_0000 0xF11C_FFFF 64 KB  
PMC_DMA1_CSR PMC DMA 1 Control reg Std 0xF11D_0000 0xF11D_FFFF 64 KB  
PMC_AES AES Module (info. provided under NDA) reg Std 0xF11E_0000 0xF11E_FFFF 64 KB  
PMC_BBRAM_CTRL Battery-backed RAM control (info. provided under NDA) reg Std 0xF11F_0000 0xF11F_FFFF 64 KB  
PMC_ECDSA_RSA ECDSA and RSA control (info. provided under NDA) reg Std 0xF120_0000 0xF120_FFFF 64 KB  
PMC_SHA3 SHA3 Module (info. provided under NDA) reg Std 0xF121_0000 0xF121_FFFF 64 KB  
PMC_SBI_CSR Boot Interface reg Std 0xF122_0000 0xF122_FFFF 64 KB  
PMC_TRNG True Random Number Generator (info. provided under NDA) reg Std 0xF123_0000 0xF123_FFFF 64 KB  
PMC_EFUSE_CTRL eFUSE Control Unit (info. partially provided under NDA) reg Std 0xF124_0000 0xF124_FFFF 64 KB  
PMC_EFUSE_CACHE eFUSE Cache (info. mostly provided under NDA) reg Std 0xF125_0000 0xF125_FFFF 64 KB  
CRP PMC Clock and Reset control reg Std 0xF126_0000 0xF126_FFFF 64 KB  
PMC_SYSMON_CSR PMC System Monitor control reg Std 0xF127_0000 0xF129_FFFF 192 KB  
PMC_RTC RTC Registers reg Std 0xF12A_0000 0xF12A_FFFF 64 KB  
CFU_CSR Configuration Frame Unit (CFU) control and status reg Std 0xF12B_0000 0xF12B_FFFF 64 KB  
CFU_SFR_mem CFU single frame read register mem Std 0xF12C_1000 0xF12C_1FFF 4 KB  
CFU_FDRO_mmap CFU frame data register output (FDRO) port Std 0xF12C_2000 0xF12C_2FFF 4 KB  
CFRAME00_CSR CFU frame 0 control and status reg Std 0xF12D_0000 0xF12D_0FFF 4 KB  
CFRAME00_FDRI CFU frame 0 data register input (FDRI) port Std 0xF12D_1000 0xF12D_1FFF 4 KB  
CFRAME01_CSR CFU frame 1 control and status reg Std 0xF12D_2000 0xF12D_2FFF 4 KB  
CFRAME01_FDRI CFU frame 1 data register input (FDRI) port Std 0xF12D_3000 0xF12D_3FFF 4 KB  
CFRAME02_CSR CFU frame 2 control and status reg Std 0xF12D_4000 0xF12D_4FFF 4 KB  
CFRAME02_FDRI CFU frame 2 data register input (FDRI) port Std 0xF12D_5000 0xF12D_5FFF 4 KB  
CFRAME03_CSR CFU frame 3 control and status reg Std 0xF12D_6000 0xF12D_6FFF 4 KB  
CFRAME03_FDRI CFU frame 3 data register input (FDRI) port Std 0xF12D_7000 0xF12D_7FFF 4 KB  
CFRAME04_CSR CFU frame 4 control and status reg Std 0xF12D_8000 0xF12D_8FFF 4 KB  
CFRAME04_FDRI CFU frame 4 data register input (FDRI) port Std 0xF12D_9000 0xF12D_9FFF 4 KB  
CFRAME05_CSR CFU frame 5 control and status reg Std 0xF12D_A000 0xF12D_AFFF 4 KB  
CFRAME05_FDRI CFU frame 5 data register input (FDRI) port Std 0xF12D_B000 0xF12D_BFFF 4 KB  
CFRAME06_CSR CFU frame 6 control and status reg Std 0xF12D_C000 0xF12D_CFFF 4 KB  
CFRAME06_FDRI CFU frame 6 data register input (FDRI) port Std 0xF12D_D000 0xF12D_DFFF 4 KB  
CFRAME07_CSR CFU frame 7 control and status reg Std 0xF12D_E000 0xF12D_EFFF 4 KB  
CFRAME07_FDRI CFU frame 7 data register input (FDRI) port Std 0xF12D_F000 0xF12D_FFFF 4 KB  
CFRAME08_CSR CFU frame 8 control and status reg Std 0xF12E_0000 0xF12E_0FFF 4 KB  
CFRAME08_FDRI CFU frame 8 data register input (FDRI) port Std 0xF12E_1000 0xF12E_1FFF 4 KB  
CFRAME09_CSR CFU frame 9 control and status reg Std 0xF12E_2000 0xF12E_2FFF 4 KB  
CFRAME09_FDRI CFU frame 9 data register input (FDRI) port Std 0xF12E_3000 0xF12E_3FFF 4 KB  
CFRAME10_CSR CFU frame 10 control and status reg Std 0xF12E_4000 0xF12E_4FFF 4 KB  
CFRAME10_FDRI CFU frame 10 data register input (FDRI) port Std 0xF12E_5000 0xF12E_5FFF 4 KB  
CFRAME11_CSR CFU frame 11 control and status reg Std 0xF12E_6000 0xF12E_6FFF 4 KB  
CFRAME11_FDRI CFU frame 11 data register input (FDRI) port Std 0xF12E_7000 0xF12E_7FFF 4 KB  
CFRAME12_CSR CFU frame 12 control and status reg Std 0xF12E_8000 0xF12E_8FFF 4 KB  
CFRAME12_FDRI CFU frame 12 data register input (FDRI) port Std 0xF12E_9000 0xF12E_9FFF 4 KB  
CFRAME13_CSR CFU frame 13 control and status reg Std 0xF12E_A000 0xF12E_AFFF 4 KB  
CFRAME13_FDRI CFU frame 13 data register input (FDRI) port Std 0xF12E_B000 0xF12E_BFFF 4 KB  
CFRAME14_CSR CFU frame 14 control and status reg Std 0xF12E_C000 0xF12E_CFFF 4 KB  
CFRAME14_FDRI CFU frame 14 data register input (FDRI) port Std 0xF12E_D000 0xF12E_DFFF 4 KB  
CFRAME_BCAST_CSR CFU frame broadcast control and status reg Std 0xF12E_E000 0xF12E_EFFF 4 KB  
CFRAME_BCAST_FDRI CFU frame broadcast data register input (FDRI) port Std 0xF12E_F000 0xF12E_FFFF 4 KB  
PMC_XMPU PMC Memory Protection Unit for PMC RAM and SBI reg Std 0xF12F_0000 0xF12F_FFFF 64 KB  
PMC_NPI_XPPU NPI Host Memory Protection Unit reg Std 0xF130_0000 0xF130_FFFF 64 KB  
PMC_XPPU PMC Peripheral Protection Unit reg Std 0xF131_0000 0xF131_FFFF 64 KB  
PMC_INT_GPV PMC Interconnect Global Programmers View (GPV) reg Std 0xF132_0000 0xF132_FFFF 64 KB  
PMC_INT_CSR PMC reset and isolation interconnect ports reg Std 0xF133_0000 0xF15A_FFFF 2.5 MB  
CFU_STREAM_port CFU Stream port Std 0xF1F8_0000 0xF1FB_FFFF 256 KB  
PMC_RAM_mem PMC RAM (128 KB) - Note: The usage of this memory is defined by the PLM. mem Std 0xF200_0000 0xF201_FFFF 128 KB  
PLM_RTCA Real-time Configuration Area - Note: Location is in the PMC RAM mreg Std 0xF201_4000 0xF201_4FFF 4 KB PMC_XMPU
SSIT_COMM SSIT Communication Area - Note: Location is in the PMC RAM mreg Opt 0xF201_5000 0xF201_5FFF 4 KB PMC_XMPU
PMC_SBI_STREAM_mem SBI Stream memory mem Std 0xF210_0000 0xF210_FFFF 64 KB  
NPI_mmap NPI Host controller memory space mem Std 0xF600_0000 0xF7FF_FFFF 32 MB  
DBG_STM_mem Coresight Debug System Trace Macrocell mem Std 0xF800_0000 0xF8FF_FFFF 16 MB  
RPU_GIC RPU general interrupt register modules, PL390, local access local Std 0xF900_0000 0xF900_2FFF 12 KB  
APU_GIC_DIST_MAIN APU general interrupt register modules, GIC-500, PL390, local access local Std 0xF900_0000 0xF900_FFFF 64 KB  
APU_GIC_DIST_MBSPI APU GIC SPI Interrupt Distributor local Std 0xF901_0000 0xF901_FFFF 64 KB  
APU_GIC_ITS_CTL APU GIC ITS control local Std 0xF902_0000 0xF902_FFFF 64 KB  
APU_GIC_ITS_TRANS APU GIC ITS service (translator) accessed only by CPM local Std 0xF903_0000 0xF903_FFFF 64 KB  
APU_GIC_CPUIF APU GIC CPU Interface local Std 0xF904_0000 0xF904_FFFF 64 KB  
APU_GIC_VIFCTL APU GIC CPU Virtual Interface Control local Std 0xF905_0000 0xF905_FFFF 64 KB  
APU_GIC_VCPUIF APU GIC CPU Virtual Interface local Std 0xF906_0000 0xF906_FFFF 64 KB  
APU_GIC_REDIST_CTLLPI_0 APU 0 GIC Redistributor control and Physical LPI local Std 0xF908_0000 0xF908_FFFF 64 KB  
APU_GIC_REDIST_SGISPI_0 APU 0 GIC Redistributor for SGI and PPI local Std 0xF909_0000 0xF909_FFFF 64 KB  
APU_GIC_REDIST_CTLLPI_1 APU 1 GIC Redistributor control and Physical LPI local Std 0xF90A_0000 0xF90A_FFFF 64 KB  
APU_GIC_REDIST_SGISPI_1 APU 1 GIC Redistributor for SGI and PPI local Std 0xF90B_0000 0xF90B_FFFF 64 KB  
CPM4_CMN CPM4 CMN Registers reg CPM4 0xFC00_0000 0xFC9F_FFFF 10 MB  
CPM4_CRX CPM4 Clock and Reset Controllers reg Opt 0xFCA0_0000 0xFCBF_FFFF 64 KB  
CPM4_SLCR CPM4 System-level Control and Status reg Opt 0xFCA1_0000 0xFCA1_FFFF 64 KB  
CPM4_SLCR_SECURE CPM4 System-level Control and Status (secure) reg Opt 0xFCA2_0000 0xFCA2_FFFF 64 KB  
CPM4_PCIE0_ATTR CPM4 PCIe0 Attributes (program with design tools) reg Opt 0xFCA5_0000 0xFCA5_FFFF 64 KB  
CPM4_PCIE1_ATTR CPM4 PCIe1 Attributes (program with design tools) reg Opt 0xFCA6_0000 0xFCA6_FFFF 64 KB  
CPM4_DMA_ATTR CPM4 PCIe DMA Attributes (program with design tools) reg Opt 0xFCA7_0000 0xFCA7_FFFF 64 KB  
CPM4_INT_GPV CPM4 Interconnect Global Programming View (GPV) reg Opt 0xFCB0_0000 0xFCB0_FFFF 128 KB  
CPM4_INT_CSR CPM4 Interconnect Contrl and Status reg Opt 0xFCB4_0000 0xFCB0_FFFF 1.5 MB  
CPM4_L2_CSR CPM2 L2 Cache Control and Status reg Opt 0xFCD0_0000 0xFCD7_FFFF 512 KB  
CPM4_ADDRREMAP CPM4 Re-map Control reg Opt 0xFCF3_0000 0xFCF3_FFFF 64 KB  
CPM4_DVSEC_0 CPM4 DVSEC 0 Buffer reg Opt 0xFCFB_0000 0xFCFB_FFFF 64 KB  
CPM4_DVSEC_1 CPM4 DVSEC 1 Buffer reg Opt 0xFCFC_0000 0xFCFC_FFFF 64 KB  
CPM4_PCIe_DMA CPM DMA control and status reg Opt 0xFCFE_0000 0xFCFE_FFFF 64 KB  
CPM4_CSR CPM control and status reg Opt 0xFCFF_0000 0xFCFF_FFFF 64 KB  
FPD_CCI_CORE Cache Coherent Interconnect (CCI-500) in FPD reg Std 0xFD00_0000 0xFD0F_FFFF 1 MB  
CRF FPD Clock and Reset controller reg Std 0xFD1A_0000 0xFD2D_FFFF 1.25 MB  
PL_AXI_FPD_CSR PL to PS AXI Interface control reg Std 0xFD36_0000 0xFD36_FFFF 64 KB  
FPD_INT_CSR FPD Interconnect control, wrapper reg Std 0xFD37_0000 0xFD37_FFFF 64 KB  
PL_ACELITE_FPD_CSR PL to PS Coherent AXI control reg Std 0xFD38_0000 0xFD38_FFFF 64 KB  
FPD_XMPU Memory Protection Unit for APU GIC and other FPD destinations reg Std 0xFD39_0000 0xFD39_FFFF 64 KB  
FPD_SWDT FPD System Watchdog Timer reg Std 0xFD4D_0000 0xFD4D_FFFF 64 KB  
APU_DUAL_CSR APU control and status reg Std 0xFD5C_0000 0xFD5C_FFFF 64 KB  
FPD_CCI_CSR Cache Coherent Interconnect reg Std 0xFD5E_0000 0xFD5E_FFFF 64 KB  
FPD_SMMU_CSR System Memory Management Unit reg Std 0xFD5F_0000 0xFD5F_FFFF 64 KB  
FPD_SLCR FPD System-level Control reg Std 0xFD61_0000 0xFD61_FFFF 64 KB  
FPD_SLCR_SECURE FPD System-level Control (secure) reg Std 0xFD69_0000 0xFD69_FFFF 64 KB  
FPD_INT_GPV FPD Interconnect Global Programmers View (GPV) reg Std 0xFD70_0000 0xFD7F_FFFF 1 MB  
FPD_SMMU SMMU core (non-secure 8 MB space) reg Std 0xFD80_0000 0xFDFF_FFFF 8 MB  
FPD_SMMU_SECURE SMMU core (secure 8 MB space) reg Std 0xFD80_0000 0xFDFF_FFFF 8 MB  
LPD_IOP_INT_GPV LPD IOP Interconnect Global Programmers View (GPV) reg Std 0xFE00_0000 0xFE0F_FFFF 1 MB LPD_XPPU (1MB a384)
USB_XHCI USB 2.0 XHCI registers reg Std 0xFE20_0000 0xFE2F_FFFF 1 MB LPD_XPPU (1MB a386)
LPD_INT_GPV LPD Interconnect Global Programmers View (GPV) reg Std 0xFE40_0000 0xFE41_FFFF 128 KB LPD_XPPU (1MB a388)
DPC_DMA_CSR Debug Port Controller DMA unit reg Std 0xFE5F_0000 0xFE5F_FFFF 64 KB LPD_XPPU (1MB a389)
LPD_INT_CSR LPD Interconnect Timeout, Reset, and Isolation reg Std 0xFE60_0000 0xFE7F_FFFF 2 MB LPD_XPPU (1MB a390)
XRAM_mem On-chip Accelerator RAM (4 banks) 4 MB total mem XRAM 0xFE80_0000 0xFEBF_FFFF 4 MB LPD_XPPU (1MB a392)
UART0 UART 0 controller reg Std 0xFF00_0000 0xFF00_FFFF 64 KB LPD_XPPU (64KB a0)
UART1 UART 1 controller reg Std 0xFF01_0000 0xFF01_FFFF 64 KB LPD_XPPU (64KB a1)
LPD_I2C0 Inter-integrated Circuit controller 0 reg Std 0xFF02_0000 0xFF02_FFFF 64 KB LPD_XPPU (64KB a2)
LPD_I2C1 Inter-integrated Circuit controller 1 reg Std 0xFF03_0000 0xFF03_FFFF 64 KB LPD_XPPU (64KB a3)
SPI0 Serial Peripheral Interface 0 reg Std 0xFF04_0000 0xFF04_FFFF 64 KB LPD_XPPU (64KB a4)
SPI1 Serial Peripheral Interface 1 reg Std 0xFF05_0000 0xFF05_FFFF 64 KB LPD_XPPU (64KB a5)
CANFD0 Controller Area Network 0 reg Std 0xFF06_0000 0xFF06_FFFF 64 KB LPD_XPPU (64KB a6)
CANFD1 Controller Area Network 1 reg Std 0xFF07_0000 0xFF07_FFFF 64 KB LPD_XPPU (64KB a7)
LPD_IOP_SLCR LPD IOP System-level Control reg Std 0xFF08_0000 0xFF09_FFFF 128 KB LPD_XPPU (64KB a8-9)
LPD_IOP_SLCR_SECURE LPD IOP System-level Control, secure reg Std 0xFF0A_0000 0xFF0A_FFFF 64 KB LPD_XPPU (64KB a10)
LPD_GPIO LPD General Purpose I/O reg Std 0xFF0B_0000 0xFF0B_FFFF 64 KB LPD_XPPU (64KB a11)
GEM0 Gigabit Ethernet MAC (GEM) controller 0 reg Std 0xFF0C_0000 0xFF0C_FFFF 64 KB LPD_XPPU (64KB a12)
GEM1 Gigabit Ethernet MAC (GEM) controller 1 reg Std 0xFF0D_0000 0xFF0D_FFFF 64 KB LPD_XPPU (64KB a13)
TTC0 Triple Timer Counter 0 reg Std 0xFF0E_0000 0xFF0E_FFFF 64 KB LPD_XPPU (64KB a14)
TTC1 Triple Timer Counter 1 reg Std 0xFF0F_0000 0xFF0F_FFFF 64 KB LPD_XPPU (64KB a15)
TTC2 Triple Timer Counter 2 reg Std 0xFF10_0000 0xFF10_FFFF 64 KB LPD_XPPU (64KB a16)
TTC3 Triple Timer Counter 3 reg Std 0xFF11_0000 0xFF11_FFFF 64 KB LPD_XPPU (64KB a17)
LPD_SWDT LPD System Watchdog Timer reg Std 0xFF12_0000 0xFF12_FFFF 64 KB LPD_XPPU (64KB a18)
SYS_COUNT_READ System software counter read reg Std 0xFF13_0000 0xFF13_FFFF 64 KB LPD_XPPU (64KB a19)
SYS_COUNT_CSR System software counter control and status reg Std 0xFF14_0000 0xFF14_FFFF 64 KB LPD_XPPU (64KB a20)
IPI Inter-processor Interrupts reg Std 0xFF30_0000 0xFF3F_FFFF 1 MB LPD_XPPU (64KB a)
LPD_SLCR LPD System-level control reg Std 0xFF41_0000 0xFF50_FFFF 1 MB LPD_XPPU (64KB a)
LPD_SLCR_SECURE LPD System-level control, secure reg Std 0xFF51_0000 0xFF54_FFFF 256 KB LPD_XPPU (64KB a)
CRL LPD Clock and Reset controller reg Std 0xFF5E_0000 0xFF8D_FFFF 3 MB LPD_XPPU (64KB a)
XRAM_CTRL0 XRAM Bank 0 control reg XRAM 0xFF8E_0000 0xFF8E_FFFF 64 KB LPD_XPPU (64KB a142)
XRAM_CTRL1 XRAM Bank 1 control reg XRAM 0xFF8F_0000 0xFF8F_FFFF 64 KB LPD_XPPU (64KB a)
XRAM_CTRL2 XRAM Bank 2 control reg XRAM 0xFF90_0000 0xFF90_FFFF 64 KB LPD_XPPU (64KB a)
XRAM_CTRL3 XRAM Bank 3 control reg XRAM 0xFF91_0000 0xFF91_FFFF 64 KB LPD_XPPU (64KB a)
XRAM_XMPU0 XRAM Memory Protection Unit 0 reg XRAM 0xFF93_0000 0xFF93_3FFF 16 KB LPD_XPPU (64KB a)
XRAM_XMPU1 XRAM Memory Protection Unit 1 reg XRAM 0xFF93_4000 0xFF93_7FFF 16 KB LPD_XPPU (64KB a)
XRAM_XMPU2 XRAM Memory Protection Unit 2 reg XRAM 0xFF93_8000 0xFF93_BFFF 16 KB LPD_XPPU (64KB a)
XRAM_XMPU3 XRAM Memory Protection Unit 3 reg XRAM 0xFF93_C000 0xFF93_FFFF 16 KB LPD_XPPU (64KB a)
XRAM_INT_GPV XRAM Interconnect Global Programmers View (GPV) reg XRAM 0xFF94_0000 0xFF94_FFFF 64 KB LPD_XPPU (64KB a)
XRAM_SLCR XRAM System-level control reg XRAM 0xFF95_0000 0xFF95_FFFF 64 KB LPD_XPPU (64KB a)
OCM_CSR On-chip Memory control reg Std 0xFF96_0000 0xFF96_FFFF 64 KB LPD_XPPU (64KB a)
OCM_XMPU OCM Memory Protection control reg Std 0xFF98_0000 0xFF98_FFFF 64 KB LPD_XPPU (64KB a)
LPD_XPPU LPD Peripheral Protection control reg Std 0xFF99_0000 0xFF99_FFFF 64 KB LPD_XPPU (64KB a)
RPU_DUAL_CSR RPU control and status reg Std 0xFF9A_0000 0xFF9A_FFFF 64 KB LPD_XPPU (64KB a)
PL_AXI_LPD_CSR PL to PS 128-bit AXI Channel reg Std 0xFF9B_0000 0xFF9B_FFFF 64 KB LPD_XPPU (64KB a)
DPC_AURORA Aurora Debug Interface reg Std 0xFF9C_0000 0xFF9C_FFFF 64 KB LPD_XPPU (64KB a)
USB_CSR USB 2.0 control in LPD reg Std 0xFF9D_0000 0xFF9D_FFFF 64 KB LPD_XPPU (64KB a)
LPD_DMA_CH0 General purpose DMA channel 0 reg Std 0xFFA8_0000 0xFFA8_FFFF 64 KB LPD_XPPU (64KB a)
LPD_DMA_CH1 General purpose DMA channel 1 reg Std 0xFFA9_0000 0xFFA9_FFFF 64 KB LPD_XPPU (64KB a)
LPD_DMA_CH2 General purpose DMA channel 2 reg Std 0xFFAA_0000 0xFFAA_FFFF 64 KB LPD_XPPU (64KB a)
LPD_DMA_CH3 General purpose DMA channel 3 reg Std 0xFFAB_0000 0xFFAB_FFFF 64 KB LPD_XPPU (64KB a)
LPD_DMA_CH4 General purpose DMA channel 4 reg Std 0xFFAC_0000 0xFFAC_FFFF 64 KB LPD_XPPU (64KB a)
LPD_DMA_CH5 General purpose DMA channel 5 reg Std 0xFFAD_0000 0xFFAD_FFFF 64 KB LPD_XPPU (64KB a)
LPD_DMA_CH6 General purpose DMA channel 6 reg Std 0xFFAE_0000 0xFFAE_FFFF 64 KB LPD_XPPU (64KB a)
LPD_DMA_CH7 General purpose DMA channel 7 reg Std 0xFFAF_0000 0xFFAF_FFFF 64 KB LPD_XPPU (64KB a)
PSM_ICACHE_mem PSM I-cache Addressable mem Std 0xFFC0_0000 0xFFC1_FFFF 128 KB LPD_XPPU (64KB a)
PSM_DCACHE_mem PSM D-cache Addressable mem Std 0xFFC2_0000 0xFFC3_FFFF 128 KB LPD_XPPU (64KB a)
PSM_IOMODULE PSM I/O Module registers reg Std 0xFFC8_0000 0xFFC8_7FFF 32 KB LPD_XPPU (64KB a)
PSM_LOCAL PSM Local registers reg Std 0xFFC8_8000 0xFFC8_FFFF 32 KB LPD_XPPU (64KB a)
PSM_GLOBAL PSM Global registers reg Std 0xFFC9_0000 0xFFC9_EFFF 60 KB LPD_XPPU (64KB a)
PSM_INT_GPV PSM Interconnect Global Programmers View (GPV) reg Std 0xFFC9_F000 0xFFC9_FFFF 4 KB LPD_XPPU (64KB a)
PSM_ICACHE_ECC PSM I-cache ECC control reg Std 0xFFCA_0000 0xFFCA_FFFF 64 KB LPD_XPPU (64KB a)
PSM_DCACHE_ECC PSM D-cache ECC control reg Std 0xFFCB_0000 0xFFCB_FFFF 64 KB LPD_XPPU (64KB a)
PSM_TMR_MANAGER PSM Triple Redundancy Manager reg Std 0xFFCC_0000 0xFFCC_FFFF 64 KB LPD_XPPU (64KB a)
PSM_TMR_INJECT PSM Triple Redundancy Error Injection reg Std 0xFFCD_0000 0xFFCD_FFFF 64 KB LPD_XPPU (64KB a)
PSM_TMR_TRACE PSM Trace Module control reg Std 0xFFCE_0000 0xFFCE_FFFF 64 KB LPD_XPPU (64KB a)
PSM_MDM PSM Debug Module control reg Std 0xFFCF_0000 0xFFCF_FFFF 64 KB LPD_XPPU (64KB a)
OCM_mem On-chip Memory space mem Std 0xFFFC_0000 0xFFFF_FFFF 256 KB LPD_XPPU (64KB a)
RPU0_TCMA_mem RPU0 TCM A lock-step and dual modes mem Std 0xFFE0_0000 0xFFE0_FFFF 64 KB LPD_XPPU (64KB a)
RPU0_TCMA_mem_lockstep RPU0 TCM A lock-step mode mem Std 0xFFE1_0000 0xFFE1_FFFF 64 KB LPD_XPPU (64KB a)
RPU0_TCMB_mem RPU0 TCM B lock-step and dual modes mem Std 0xFFE2_0000 0xFFE2_FFFF 64 KB LPD_XPPU (64KB a)
RPU0_TCMB_mem_lockstep RPU0 TCM B lock-step mode mem Std 0xFFE3_0000 0xFFE3_FFFF 64 KB LPD_XPPU (64KB a)
RPU0_ICACHE_mem RPU0 instruction cache lock-step and dual modes mem Std 0xFFE4_0000 0xFFE4_7FFF 32 KB LPD_XPPU (64KB a)
RPU0_DCACHE_mem RPU0 data cache lock-step and dual modes mem Std 0xFFE5_0000 0xFFE5_7FFF 32 KB LPD_XPPU (64KB a)
RPU1_TCMA_mem_dual RPU1 TCM A dual mode mem Std 0xFFE9_0000 0xFFE9_FFFF 64 KB LPD_XPPU (64KB a)
RPU1_TCMB_mem_dual RPU1 TCM B dual mode mem Std 0xFFEB_0000 0xFFEB_FFFF 64 KB LPD_XPPU (64KB a)
RPU1_ICACHE_mem_dual RPU1 instruction cache dual mode mem Std 0xFFEC_0000 0xFFED_7FFF 32 KB LPD_XPPU (64KB a)
RPU1_DCACHE_mem_dual RPU1 data cache dual mode mem Std 0xFFED_0000 0xFFED_7FFF 32 KB LPD_XPPU (64KB a)
CPM5_PCIe0_mem CPM5 Interconnect to CPM5 APB switch mem CPM5 0xE000_0000 0xEFFF_FFFF 256 MB -
CPM5_INT_GPV CPM5 Global Programmer's View Interconnect control reg CPM5 0xFCD8_0000 0xFCD9_FFFF 128 -
CPM5_ADDRREMAP CPM5 Address ReMap control reg CPM5 0xFCDB_0000 0xFCDB_FFFF 64 KB -
CPM5_CRX CPM5 Clock and Reset registers reg CPM5 0xFCDC_0000 0xFCDC_FFFF 64 KB -
CPM5_SLCR CPM5 System-level Control Registers reg CPM5 0xFCDD_0000 0xFCDD_FFFF 64 KB -
CPM5_SLCR_SECURE CPM5 Secure System-level Control Registers reg CPM5 0xFCDE_0000 0xFCDE_FFFF 64 KB -
CPM5_PCIE0_CSR CPM5 PCIe Controller 0 Control and Status reg CPM5 0xFCE0_0000 0xFCE0_7FFF 32 KB -
CPM5_PCIE0_ATTR CPM5 PCIe Controller 0 Attributes reg CPM5 0xFCE0_8000 0xFCE0_FFFF 32 KB -
CPM5_DMA0_ATTR CPM5 DMA Controller 0 Attributes reg CPM5 0xFCE1_0000 0xFCE1_FFFF 64 KB -
CPM5_DMA0_CSR CPM5 DMA Controller 0 Control and Status reg CPM5 0xFCE2_0000 0xFCE2_FFFF 64 KB -
CPM5_DPLL0_ATTR CPM5 Digital PLL 0 Control reg CPM5 0xFCE3_0000 0xFCE3_FFFF 64 KB -
CPM5_DVSEC0 CPM5 Device Security Controller 0 reg CPM5 0xFCE4_0000 0xFCE4_FFFF 64 KB -
CPM5_PCIE1_CSR CPM5 PCIe Controller 1 Control and Status reg CPM5 0xFCE8_0000 0xFCE8_7FFF 32 KB -
CPM5_PCIE1_ATTR CPM5 PCIe Controller 1 Attributes reg CPM5 0xFCE8_8000 0xFCE8_FFFF 32 KB -
CPM5_DMA1_ATTR CPM5 DMA Controller 1 Attributes reg CPM5 0xFCE9_0000 0xFCE9_FFFF 64 KB -
CPM5_DMA1_CSR CPM5 DMA Controller 1 Control and Status reg CPM5 0xFCEA_0000 0xFCEA_FFFF 64 KB -
CPM5_DPLL1_ATTR CPM5 Digital PLL 1 Control reg CPM5 0xFCEB_0000 0xFCEB_FFFF 64 KB -
CPM5_DVSEC1 CPM5 Device Security Controller 1 reg CPM5 0xFCEC_0000 0xFCEC_FFFF 64 KB -
CPM5_CMN CPM5 Cache Mesh Network Registers reg CPM5 0xFC00_0000 0xFC9F_FFFF 10 MB -
CPM5_CRX CPM5 Clock and Reset Registers reg CPM5 0xFCA0_0000 0xFCBF_FFFF 2 MB -
CPM5_L20_CSR CPM5 L2 Cache 0 Control and Status reg CPM5 0xFCC0_0000 0xFCC7_FFFF 512 KB -
CPM5_L21_CSR CPM5 L2 Cache 1 Control and Status reg CPM5 0xFCC8_0000 0xFCCF_FFFF 512 KB -
CPM5_PCSR CPM5 Control and Status Registers reg CPM5 0xFCFF_0000 0xFCFF_FFFF 64 KB -