DLL Programming Model

There are two parts to programming the DLL.

• Program the DLL reference clock source (shared with both controllers)
• Program the DLL module in the SD_eMMC controller

DLL Reference Clock

DLL reference clock controls are in the CRP-based SDIO_DLL_REF_CTRL register.

• Select PLL source: [SRCSEL] bit field
• Set 10-bit divisor: [DIVISOR] bit field
• Enable the clock: [CLKACT] bit field

DLL Module

The clock delays for the RX and TX interface units are imposed by selecting delay taps in the DLL module. The maximum number of delay taps is 180. At a high frequency, the typical number of tap delays is much smaller. The lower the frequency, the more taps available.

DLL module control registers are in the SD_eMMU register module.

• CLK_CTRL register fields:
  • [SDClkFreqDiv_H,7:6]
  • [SDClkFreqDiv_L, 15:8]
• register field: [sel, 7:0]
• register field: [sel, 5:0]

DLL Clock Settings

The DLL clock settings are listed in the following table.