Table: DMA Controller Registers is an overview of the DMA controller registers.
Table 19-5: DMA Controller Registers
Register Name
|
Description
|
ZDMA_ERR_CTRL
|
Enable/disable an error response.
|
ZDMA_CH_ISR
|
Interrupt status register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.
|
ZDMA_CH_IMR
|
Interrupt mask register for intrN. This is a read-only location and can be automatically altered by either the IDS or the IEN.
|
ZDMA_CH_IEN
|
Interrupt enable register. A write of 1 to this location will unmask the interrupt. (IMR: 0).
|
ZDMA_CH_IDS
|
Interrupt disable register. A write of 1 to this location will mask the interrupt. (IMR: 1).
|
ZDMA_CH_CTRL0
|
Channel control register 0.
|
ZDMA_CH_CTRL1
|
Channel control register 1.
|
ZDMA_CH_FCI
|
Channel flow control register.
|
ZDMA_CH_STATUS
|
Channel status register.
|
ZDMA_CH_DATA_ATTR
|
Channel DATA AXI parameter register.
|
ZDMA_CH_DSCR_ATTR
|
Channel DSCR AXI parameter register.
|
ZDMA_CH_SRC_DSCR_WORD0
|
SRC DSCR word 0.
|
ZDMA_CH_SRC_DSCR_WORD1
|
SRC DSCR word 1.
|
ZDMA_CH_SRC_DSCR_WORD2
|
SRC DSCR word 2.
|
ZDMA_CH_SRC_DSCR_WORD3
|
SRC DSCR word 3.
|
ZDMA_CH_DST_DSCR_WORD0
|
DST DSCR word 0.
|
ZDMA_CH_DST_DSCR_WORD1
|
DST DSCR word 1.
|
ZDMA_CH_DST_DSCR_WORD2
|
DST DSCR word 2.
|
ZDMA_CH_DST_DSCR_WORD3
|
DST DSCR word 3.
|
ZDMA_CH_WR_ONLY_WORD0
|
Write-only data word 0.
|
ZDMA_CH_WR_ONLY_WORD1
|
Write-only data word 1.
|
ZDMA_CH_WR_ONLY_WORD2
|
Write-only data word 2.
|
ZDMA_CH_WR_ONLY_WORD3
|
Write-only data word 3.
|
ZDMA_CH_SRC_START_LSB
|
SRC DSCR start address LSB register.
|
ZDMA_CH_SRC_START_MSB
|
SRC DSCR start address MSB register.
|
ZDMA_CH_DST_START_LSB
|
DST DSCR start address LSB register.
|
ZDMA_CH_DST_START_MSB
|
DST DSCR start address MSB register.
|
ZDMA_CH_RATE_CTRL
|
Rate control count register.
|
ZDMA_CH_IRQ_SRC_ACCT
|
SRC interrupt account count register.
|
ZDMA_CH_IRQ_DST_ACCT
|
DST interrupt account count register.
|
ZDMA_CH_CTRL2
|
DMA control register 2.
|