Table: SWDT Register Overview is an overview of the SWDT registers, SWDT, WDT, and CSU_WDT register sets. Table 14-14: SWDT Register Overview Offset Name Access Bits Description 0x00 Watchdog zero mode register state on reset: 0x1C2 Read/Write 0 WDEN: Watchdog enable. If set, the watchdog is enabled and can generate enabled signals. 1 RSTEN: Reset enable. If set, the watchdog issues an internal reset when the counter reaches zero, if WDEN = 1. 2 IRQEN: Interrupt request enable. If set, the watchdog issues an interrupt request when the counter reaches zero, if WDEN = 1. 3 Reserved. 6:4 RSTLN: Reset length, 2 to 256 PCLK cycles. 8:7 IRQLN: Interrupt request length, 4 to 32 PCLK cycles. 11:9 Should be zero (sbz). Write only 23:12 ZKEY: Zero access key. Writes to the zero mode register are only valid if this field is 0xABC. 0x04 Counter control register state on reset: 0b111100 Read/Write 1:0 CLKSEL: Counter clock prescale, from PCLK/8 to PCLK/4096. 13:2 CRV: Counter restart value. The counter is restarted with 0xNFFF, where N is the value of this field. Write only 25:14 CKEY: Counter access key. Writes to the control register are only valid if this field is 0x248. 0x08 Restart register Write only 15:0 RSTKEY: Restart key. The watchdog is restarted if this field is set to 0x1999. 0x0C Status register state on reset: 0x00 Read only 0 WDZ: Watchdog zero. This bit is set when the counter reaches zero.