Table: Encoding for DDRC.ECCSTAT [corrected_bit_num] provides the encoding used for the status register field DDRC.ECCSTAT [corrected_bit_num] which indicates the bit that is corrected.
Table 17-8: Encoding for DDRC.ECCSTAT [corrected_bit_num]
|
Value on DDRC.ECCSTAT[corrected_bit_num]
|
Bit that has Error
|
|
DRAM Bus Width = 64
|
DRAM Bus Width = 32
|
|
0
|
64 (ecc[0])
|
64 (ecc[0])
|
|
1
|
65 (ecc[1])
|
65 (ecc[1])
|
|
2
|
66 (ecc[2])
|
66 (ecc[2])
|
|
3
|
0
|
0
|
|
4
|
67 (ecc[3])
|
67 (ecc[3])
|
|
5
|
1
|
1
|
|
6
|
2
|
2
|
|
7
|
3
|
3
|
|
8
|
68 (ecc[4])
|
68 (ecc[4])
|
|
9
|
4
|
4
|
|
10
|
5
|
5
|
|
…
|
…
|
…
|
|
15
|
10
|
10
|
|
16
|
69 (ecc[5])
|
69 (ecc[5])
|
|
17
|
11
|
11
|
|
18
|
12
|
12
|
|
…
|
…
|
…
|
|
21
|
15
|
15
|
|
22
|
16
|
16
|
|
…
|
…
|
…
|
|
31
|
25
|
25
|
|
32
|
70 (ecc[6])
|
70 (ecc[6])
|
|
33
|
26
|
26
|
|
34
|
27
|
27
|
|
…
|
…
|
…
|
|
38
|
31
|
31
|
|
39
|
32
|
NA
|
|
…
|
…
|
…
|
|
63
|
56
|
NA
|
|
64
|
71 (ecc[7])
|
71 (ecc[7])
|
|
65
|
57
|
NA
|
|
66
|
58
|
NA
|
|
…
|
…
|
…
|
|
71
|
63
|
NA
|