|
Task
|
Register
|
Register Field
|
Register Offset
|
Bits
|
Value (Binary)
|
|
Enable buffer read ready interrupt.
|
Interrupt_Status_Enable_Register
|
buff_rd_rdy_sts_en
|
0x014
|
1
|
1b'1
|
|
Program read parameter page command (0xEC) with no ECC, no DMA, and one address cycle.
|
Command_Register
|
All
|
0x0C
|
31:0
|
0x010000EC
|
|
Program column, page, and block address (next two steps).
|
|
Program memory address register 1.
|
Memory_Address_Register1
|
All
|
0x04
|
31:0
|
•Program block address in bits 31:25.
•Program page address in bits 22:16.
•Program column address in 12:0 bits.
|
|
Program memory address register 2.
|
Memory_Address_Register2
|
All
|
0x008
|
31:0
|
Write required values for memory address.
|
|
Select the device.
|
Memory_Address_Register2
|
Chip_Select
|
0x08
|
31:30
|
Targets chip select value.
|
|
Select packet size and count (256).
|
Packet_Register
|
Packet_count | packet_size
|
0x00
|
23:0
|
Required packet size and count.
|
|
Set read parameter page in program register.
|
Program_Register
|
Read_Parameter_Page
|
0x10
|
7
|
1b'1
|
|
Poll for buffer read ready event.
|
Interrupt_Status_Register
|
buff_rd_rdy_reg
|
0x1C
|
1
|
Wait until bit is set or wait time over.
|
|
Enable the transmit complete interrupt after transfer completed.
|
Interrupt_Status_Enable_Register
|
trans_comp_sts_en
|
0x014
|
2
|
1b'1
|
|
Clear buffer read ready interrupt.
|
Interrupt_Status_Register
|
buff_rd_rdy_reg
|
0x1C
|
1
|
1b'1
|
|
Read packet data.
|
Buffer_Data_Port_Register
|
Data_Port_Register
|
0x030
|
31:0
|
Read until all data received.
|
|
Poll for transfer complete event.
|
Interrupt_Status_Register
|
trans_comp_reg
|
0x1C
|
2
|
Wait until transfer is completed or wait time is over.
|
|
Clear the transmit complete interrupt after transfer completed.
|
Interrupt_Status_Enable_Register
|
trans_comp_sts_en
|
0x014
|
2
|
1b'0
|
|
Clear the transmit complete flag after transfer completed.
|
Interrupt_Status_Register
|
trans_comp_reg
|
0x1C
|
2
|
1b'1
|