Graphics Processing Unit Memory Management Unit

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

All memory accesses from the pixel processor and geometry processor use memory management units (MMUs) for access checking and translation. The GPU contains several MMUs to translate and restrict memory accesses that the pixel or geometry processors initiate. An MMU is configured by writing to control registers and uses in-memory page table structures as the basis for address translation.

The MMU divides memory into 4 KB pages, where each page can be individually configured. For each page the following parameters are specified.

The physical memory address of the page. Known as address translation or virtual memory, this enables the processor to work using addresses that differ from the physical addresses in the memory system.

The permitted types of accesses to that page. Each page can permit reads, writes, both, or none.

The MMU uses a two-level page table structure (This Figure). The first level, the page directory consists of 1024 directory table entries (DTEs), each pointing to a page table. In the second level, the page table consists of 1024 page table entries (PTEs), each pointing to a page in memory.

Figure 5-6:      Structure of the Two-level Page Table

X-Ref Target - Figure 5-6


The MMU address bits are shown in Table: MMU Address Bits.

Table 5-4:      MMU Address Bits

































DTE Index

PTE Index

Page Offset

The MMU uses the following algorithm to translate an address.

1.Find the DTE at address given by MMU_DTE_ADDR + (4 x DTE index).

2.   Find the PTE at address given by (page table address from DTE) + (4 x PTE index).

3.   Calculate effective address as (page address from PTE) + (page offset).

This Figure shows various possible state transitions for the MMU.

Figure 5-7:      GPU MMU State Diagram

X-Ref Target - Figure 5-7