The XPPU aperture register structure enumerates the permission settings on each protected peripheral, message buffer, and the Quad-SPI flash memory. Each APERPERM_{000:400} register entry contains the information listed in Table: Aperture Permissions Register Format.
Four parity bits are added to protect the (TrustZone and permission) fields, which are equally divided into four protected fields. Parity must be computed by software when writing an entry in the aperture permission list. If the controller detects a parity error, then a status bit is set.
•Bit [31] is parity for bit [27] and bits [19:15].
•Bit [30] is parity for bits [14:10].
•Bit [29] is parity for bits [9:5].
•Bit [28] is parity for bits [4:0].
The aperture permission list must be completely initialized by software to 0 before the XPPU can be enabled. The software is also required to compute and write parity. For unprotected apertures, all supported master match bits in the permission RAM should be set to 1.